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memory.cpp
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memory.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Memory management
*
* (c) 1995 Bernd Schmidt
*/
#define DEBUG_STUPID 0
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "uae.h"
#include "memory.h"
#include "rommgr.h"
#include "ersatz.h"
#include "zfile.h"
#include "custom.h"
#include "events.h"
#include "newcpu.h"
#include "autoconf.h"
#include "savestate.h"
#include "ar.h"
#include "crc32.h"
#include "gui.h"
#include "cdtv.h"
#include "akiko.h"
#include "arcadia.h"
#include "enforcer.h"
#include "a2091.h"
#include "gayle.h"
#include "debug.h"
bool canbang;
int candirect = -1;
#ifdef JIT
/* Set by each memory handler that does not simply access real memory. */
int special_mem;
#endif
static bool isdirectjit (void)
{
return currprefs.cachesize && !currprefs.comptrustbyte;
}
static bool canjit (void)
{
if (currprefs.cpu_model < 68020 && currprefs.address_space_24)
return 0;
return 1;
}
static void nocanbang (void)
{
canbang = 0;
}
uae_u32 allocated_chipmem;
uae_u32 allocated_fastmem;
uae_u32 allocated_bogomem;
uae_u32 allocated_gfxmem;
uae_u32 allocated_z3fastmem, allocated_z3fastmem2, allocated_z3chipmem;
uae_u32 allocated_a3000lmem;
uae_u32 allocated_a3000hmem;
uae_u32 allocated_cardmem;
uae_u8 ce_banktype[65536];
uae_u8 ce_cachable[65536];
#if defined(CPU_64_BIT)
uae_u32 max_z3fastmem = 2048UL * 1024 * 1024;
#else
uae_u32 max_z3fastmem = 512 * 1024 * 1024;
#endif
static size_t bootrom_filepos, chip_filepos, bogo_filepos, rom_filepos, a3000lmem_filepos, a3000hmem_filepos;
/* Set if we notice during initialization that settings changed,
and we must clear all memory to prevent bogus contents from confusing
the Kickstart. */
static bool need_hardreset;
/* The address space setting used during the last reset. */
static bool last_address_space_24;
addrbank *mem_banks[MEMORY_BANKS];
/* This has two functions. It either holds a host address that, when added
to the 68k address, gives the host address corresponding to that 68k
address (in which case the value in this array is even), OR it holds the
same value as mem_banks, for those banks that have baseaddr==0. In that
case, bit 0 is set (the memory access routines will take care of it). */
uae_u8 *baseaddr[MEMORY_BANKS];
#ifdef NO_INLINE_MEMORY_ACCESS
__inline__ uae_u32 longget (uaecptr addr)
{
return call_mem_get_func (get_mem_bank (addr).lget, addr);
}
__inline__ uae_u32 wordget (uaecptr addr)
{
return call_mem_get_func (get_mem_bank (addr).wget, addr);
}
__inline__ uae_u32 byteget (uaecptr addr)
{
return call_mem_get_func (get_mem_bank (addr).bget, addr);
}
__inline__ void longput (uaecptr addr, uae_u32 l)
{
call_mem_put_func (get_mem_bank (addr).lput, addr, l);
}
__inline__ void wordput (uaecptr addr, uae_u32 w)
{
call_mem_put_func (get_mem_bank (addr).wput, addr, w);
}
__inline__ void byteput (uaecptr addr, uae_u32 b)
{
call_mem_put_func (get_mem_bank (addr).bput, addr, b);
}
#endif
int addr_valid (TCHAR *txt, uaecptr addr, uae_u32 len)
{
addrbank *ab = &get_mem_bank(addr);
if (ab == 0 || !(ab->flags & (ABFLAG_RAM | ABFLAG_ROM)) || addr < 0x100 || len < 0 || len > 16777215 || !valid_address (addr, len)) {
write_log (L"corrupt %s pointer %x (%d) detected!\n", txt, addr, len);
return 0;
}
return 1;
}
uae_u32 chipmem_mask, chipmem_full_mask, chipmem_full_size;
uae_u32 kickmem_mask, extendedkickmem_mask, extendedkickmem2_mask, bogomem_mask;
uae_u32 a3000lmem_mask, a3000hmem_mask, cardmem_mask;
static int illegal_count;
/* A dummy bank that only contains zeros */
static uae_u32 REGPARAM3 dummy_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 dummy_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 dummy_bget (uaecptr) REGPARAM;
static void REGPARAM3 dummy_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 dummy_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 dummy_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 dummy_check (uaecptr addr, uae_u32 size) REGPARAM;
#define MAX_ILG 200
#define NONEXISTINGDATA 0
//#define NONEXISTINGDATA 0xffffffff
static void dummylog (int rw, uaecptr addr, int size, uae_u32 val, int ins)
{
if (illegal_count >= MAX_ILG && MAX_ILG > 0)
return;
/* ignore Zorro3 expansion space */
if (addr >= 0xff000000 && addr <= 0xff000200)
return;
/* autoconfig and extended rom */
if (addr >= 0xe00000 && addr <= 0xf7ffff)
return;
/* motherboard ram */
if (addr >= 0x08000000 && addr <= 0x08000007)
return;
if (addr >= 0x07f00000 && addr <= 0x07f00007)
return;
if (addr >= 0x07f7fff0 && addr <= 0x07ffffff)
return;
if (MAX_ILG >= 0)
illegal_count++;
if (ins) {
write_log (L"WARNING: Illegal opcode %cget at %08lx PC=%x\n",
size == 2 ? 'w' : 'l', addr, M68K_GETPC);
} else if (rw) {
write_log (L"Illegal %cput at %08lx=%08lx PC=%x\n",
size == 1 ? 'b' : size == 2 ? 'w' : 'l', addr, val, M68K_GETPC);
} else {
write_log (L"Illegal %cget at %08lx PC=%x\n",
size == 1 ? 'b' : size == 2 ? 'w' : 'l', addr, M68K_GETPC);
}
}
static uae_u32 dummy_get (uaecptr addr, int size)
{
uae_u32 v;
if (currprefs.cpu_model >= 68020)
return NONEXISTINGDATA;
v = (regs.irc << 16) | regs.irc;
if (size == 4) {
;
} else if (size == 2) {
v &= 0xffff;
} else {
v = (addr & 1) ? (v & 0xff) : ((v >> 8) & 0xff);
}
#if 0
if (addr >= 0x10000000)
write_log (L"%08X %d = %08x\n", addr, size, v);
#endif
return v;
}
static uae_u32 REGPARAM2 dummy_lget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
if (currprefs.illegal_mem)
dummylog (0, addr, 4, 0, 0);
return dummy_get (addr, 4);
}
uae_u32 REGPARAM2 dummy_lgeti (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
if (currprefs.illegal_mem)
dummylog (0, addr, 4, 0, 1);
return dummy_get (addr, 4);
}
static uae_u32 REGPARAM2 dummy_wget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
if (currprefs.illegal_mem)
dummylog (0, addr, 2, 0, 0);
return dummy_get (addr, 2);
}
uae_u32 REGPARAM2 dummy_wgeti (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
if (currprefs.illegal_mem)
dummylog (0, addr, 2, 0, 1);
return dummy_get (addr, 2);
}
static uae_u32 REGPARAM2 dummy_bget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
if (currprefs.illegal_mem)
dummylog (0, addr, 1, 0, 0);
return dummy_get (addr, 1);
}
static void REGPARAM2 dummy_lput (uaecptr addr, uae_u32 l)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (currprefs.illegal_mem)
dummylog (1, addr, 4, l, 0);
}
static void REGPARAM2 dummy_wput (uaecptr addr, uae_u32 w)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (currprefs.illegal_mem)
dummylog (1, addr, 2, w, 0);
}
static void REGPARAM2 dummy_bput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (currprefs.illegal_mem)
dummylog (1, addr, 1, b, 0);
}
static int REGPARAM2 dummy_check (uaecptr addr, uae_u32 size)
{
#ifdef JIT
special_mem |= S_READ;
#endif
return 0;
}
static void REGPARAM2 none_put (uaecptr addr, uae_u32 v)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
}
static uae_u32 REGPARAM2 ones_get (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
return 0xffffffff;
}
/* Chip memory */
uae_u8 *chipmemory;
static int REGPARAM3 chipmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 chipmem_xlate (uaecptr addr) REGPARAM;
#ifdef AGA
/* AGA ce-chipram access */
static void ce2_timeout (void)
{
wait_cpu_cycle_read (0, -1);
}
static uae_u32 REGPARAM2 chipmem_lget_ce2 (uaecptr addr)
{
uae_u32 *m;
#ifdef JIT
special_mem |= S_READ;
#endif
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
ce2_timeout ();
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 chipmem_wget_ce2 (uaecptr addr)
{
uae_u16 *m, v;
#ifdef JIT
special_mem |= S_READ;
#endif
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
ce2_timeout ();
v = do_get_mem_word (m);
return v;
}
static uae_u32 REGPARAM2 chipmem_bget_ce2 (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
addr &= chipmem_mask;
ce2_timeout ();
return chipmemory[addr];
}
static void REGPARAM2 chipmem_lput_ce2 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
ce2_timeout ();
do_put_mem_long (m, l);
}
static void REGPARAM2 chipmem_wput_ce2 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
ce2_timeout ();
do_put_mem_word (m, w);
}
static void REGPARAM2 chipmem_bput_ce2 (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= chipmem_mask;
ce2_timeout ();
chipmemory[addr] = b;
}
#endif
uae_u32 REGPARAM2 chipmem_lget (uaecptr addr)
{
uae_u32 *m;
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 chipmem_wget (uaecptr addr)
{
uae_u16 *m, v;
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
v = do_get_mem_word (m);
return v;
}
static uae_u32 REGPARAM2 chipmem_bget (uaecptr addr)
{
uae_u8 v;
addr &= chipmem_mask;
v = chipmemory[addr];
return v;
}
void REGPARAM2 chipmem_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 chipmem_bput (uaecptr addr, uae_u32 b)
{
addr &= chipmem_mask;
chipmemory[addr] = b;
}
/* cpu chipmem access inside agnus addressable ram but no ram available */
static uae_u32 chipmem_dummy (void)
{
/* not really right but something random that has more ones than zeros.. */
return 0xffff & ~((1 << (rand () & 31)) | (1 << (rand () & 31)));
}
void REGPARAM2 chipmem_dummy_bput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
}
void REGPARAM2 chipmem_dummy_wput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
}
void REGPARAM2 chipmem_dummy_lput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
}
static uae_u32 REGPARAM2 chipmem_dummy_bget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
return chipmem_dummy ();
}
static uae_u32 REGPARAM2 chipmem_dummy_wget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
return chipmem_dummy ();
}
static uae_u32 REGPARAM2 chipmem_dummy_lget (uaecptr addr)
{
#ifdef JIT
special_mem |= S_READ;
#endif
return (chipmem_dummy () << 16) | chipmem_dummy ();
}
static uae_u32 REGPARAM2 chipmem_agnus_lget (uaecptr addr)
{
uae_u32 *m;
addr &= chipmem_full_mask;
m = (uae_u32 *)(chipmemory + addr);
return do_get_mem_long (m);
}
uae_u32 REGPARAM2 chipmem_agnus_wget (uaecptr addr)
{
uae_u16 *m;
addr &= chipmem_full_mask;
m = (uae_u16 *)(chipmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 chipmem_agnus_bget (uaecptr addr)
{
addr &= chipmem_full_mask;
return chipmemory[addr];
}
static void REGPARAM2 chipmem_agnus_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return;
m = (uae_u32 *)(chipmemory + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_agnus_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return;
m = (uae_u16 *)(chipmemory + addr);
do_put_mem_word (m, w);
}
static void REGPARAM2 chipmem_agnus_bput (uaecptr addr, uae_u32 b)
{
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return;
chipmemory[addr] = b;
}
static int REGPARAM2 chipmem_check (uaecptr addr, uae_u32 size)
{
addr &= chipmem_mask;
return (addr + size) <= chipmem_full_size;
}
static uae_u8 *REGPARAM2 chipmem_xlate (uaecptr addr)
{
addr &= chipmem_mask;
return chipmemory + addr;
}
STATIC_INLINE void REGPARAM2 chipmem_lput_bigmem (uaecptr addr, uae_u32 v)
{
put_long (addr, v);
}
STATIC_INLINE void REGPARAM2 chipmem_wput_bigmem (uaecptr addr, uae_u32 v)
{
put_word (addr, v);
}
STATIC_INLINE void REGPARAM2 chipmem_bput_bigmem (uaecptr addr, uae_u32 v)
{
put_byte (addr, v);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_lget_bigmem (uaecptr addr)
{
return get_long (addr);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_wget_bigmem (uaecptr addr)
{
return get_word (addr);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_bget_bigmem (uaecptr addr)
{
return get_byte (addr);
}
STATIC_INLINE int REGPARAM2 chipmem_check_bigmem (uaecptr addr, uae_u32 size)
{
return valid_address (addr, size);
}
STATIC_INLINE uae_u8* REGPARAM2 chipmem_xlate_bigmem (uaecptr addr)
{
return get_real_address (addr);
}
uae_u32 (REGPARAM2 *chipmem_lget_indirect)(uaecptr);
uae_u32 (REGPARAM2 *chipmem_wget_indirect)(uaecptr);
uae_u32 (REGPARAM2 *chipmem_bget_indirect)(uaecptr);
void (REGPARAM2 *chipmem_lput_indirect)(uaecptr, uae_u32);
void (REGPARAM2 *chipmem_wput_indirect)(uaecptr, uae_u32);
void (REGPARAM2 *chipmem_bput_indirect)(uaecptr, uae_u32);
int (REGPARAM2 *chipmem_check_indirect)(uaecptr, uae_u32);
uae_u8 *(REGPARAM2 *chipmem_xlate_indirect)(uaecptr);
static void chipmem_setindirect (void)
{
if (currprefs.z3chipmem_size) {
chipmem_lget_indirect = chipmem_lget_bigmem;
chipmem_wget_indirect = chipmem_wget_bigmem;
chipmem_bget_indirect = chipmem_bget_bigmem;
chipmem_lput_indirect = chipmem_lput_bigmem;
chipmem_wput_indirect = chipmem_wput_bigmem;
chipmem_bput_indirect = chipmem_bput_bigmem;
chipmem_check_indirect = chipmem_check_bigmem;
chipmem_xlate_indirect = chipmem_xlate_bigmem;
} else {
chipmem_lget_indirect = chipmem_lget;
chipmem_wget_indirect = chipmem_agnus_wget;
chipmem_bget_indirect = chipmem_agnus_bget;
chipmem_lput_indirect = chipmem_lput;
chipmem_wput_indirect = chipmem_agnus_wput;
chipmem_bput_indirect = chipmem_agnus_bput;
chipmem_check_indirect = chipmem_check;
chipmem_xlate_indirect = chipmem_xlate;
}
}
/* Slow memory */
static uae_u8 *bogomemory;
static int bogomemory_allocated;
static uae_u32 REGPARAM3 bogomem_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 bogomem_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 bogomem_bget (uaecptr) REGPARAM;
static void REGPARAM3 bogomem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 bogomem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 bogomem_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 bogomem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 bogomem_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM2 bogomem_lget (uaecptr addr)
{
uae_u32 *m;
addr &= bogomem_mask;
m = (uae_u32 *)(bogomemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 bogomem_wget (uaecptr addr)
{
uae_u16 *m;
addr &= bogomem_mask;
m = (uae_u16 *)(bogomemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 bogomem_bget (uaecptr addr)
{
addr &= bogomem_mask;
return bogomemory[addr];
}
static void REGPARAM2 bogomem_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= bogomem_mask;
m = (uae_u32 *)(bogomemory + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 bogomem_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= bogomem_mask;
m = (uae_u16 *)(bogomemory + addr);
do_put_mem_word (m, w);
}
static void REGPARAM2 bogomem_bput (uaecptr addr, uae_u32 b)
{
addr &= bogomem_mask;
bogomemory[addr] = b;
}
static int REGPARAM2 bogomem_check (uaecptr addr, uae_u32 size)
{
addr &= bogomem_mask;
return (addr + size) <= allocated_bogomem;
}
static uae_u8 *REGPARAM2 bogomem_xlate (uaecptr addr)
{
addr &= bogomem_mask;
return bogomemory + addr;
}
/* CDTV expension memory card memory */
uae_u8 *cardmemory;
static uae_u32 REGPARAM3 cardmem_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 cardmem_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 cardmem_bget (uaecptr) REGPARAM;
static void REGPARAM3 cardmem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 cardmem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 cardmem_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 cardmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 cardmem_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM2 cardmem_lget (uaecptr addr)
{
uae_u32 *m;
addr &= cardmem_mask;
m = (uae_u32 *)(cardmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 cardmem_wget (uaecptr addr)
{
uae_u16 *m;
addr &= cardmem_mask;
m = (uae_u16 *)(cardmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 cardmem_bget (uaecptr addr)
{
addr &= cardmem_mask;
return cardmemory[addr];
}
static void REGPARAM2 cardmem_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= cardmem_mask;
m = (uae_u32 *)(cardmemory + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 cardmem_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= cardmem_mask;
m = (uae_u16 *)(cardmemory + addr);
do_put_mem_word (m, w);
}
static void REGPARAM2 cardmem_bput (uaecptr addr, uae_u32 b)
{
addr &= cardmem_mask;
cardmemory[addr] = b;
}
static int REGPARAM2 cardmem_check (uaecptr addr, uae_u32 size)
{
addr &= cardmem_mask;
return (addr + size) <= allocated_cardmem;
}
static uae_u8 *REGPARAM2 cardmem_xlate (uaecptr addr)
{
addr &= cardmem_mask;
return cardmemory + addr;
}
/* A3000 motherboard fast memory */
static uae_u8 *a3000lmemory, *a3000hmemory;
uae_u32 a3000lmem_start, a3000hmem_start;
static uae_u32 REGPARAM3 a3000lmem_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 a3000lmem_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 a3000lmem_bget (uaecptr) REGPARAM;
static void REGPARAM3 a3000lmem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 a3000lmem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 a3000lmem_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 a3000lmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 a3000lmem_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM2 a3000lmem_lget (uaecptr addr)
{
uae_u32 *m;
addr &= a3000lmem_mask;
m = (uae_u32 *)(a3000lmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 a3000lmem_wget (uaecptr addr)
{
uae_u16 *m;
addr &= a3000lmem_mask;
m = (uae_u16 *)(a3000lmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 a3000lmem_bget (uaecptr addr)
{
addr &= a3000lmem_mask;
return a3000lmemory[addr];
}
static void REGPARAM2 a3000lmem_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= a3000lmem_mask;
m = (uae_u32 *)(a3000lmemory + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 a3000lmem_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= a3000lmem_mask;
m = (uae_u16 *)(a3000lmemory + addr);
do_put_mem_word (m, w);
}
static void REGPARAM2 a3000lmem_bput (uaecptr addr, uae_u32 b)
{
addr &= a3000lmem_mask;
a3000lmemory[addr] = b;
}
static int REGPARAM2 a3000lmem_check (uaecptr addr, uae_u32 size)
{
addr &= a3000lmem_mask;
return (addr + size) <= allocated_a3000lmem;
}
static uae_u8 *REGPARAM2 a3000lmem_xlate (uaecptr addr)
{
addr &= a3000lmem_mask;
return a3000lmemory + addr;
}
static uae_u32 REGPARAM3 a3000hmem_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 a3000hmem_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 a3000hmem_bget (uaecptr) REGPARAM;
static void REGPARAM3 a3000hmem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 a3000hmem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 a3000hmem_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 a3000hmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 a3000hmem_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM2 a3000hmem_lget (uaecptr addr)
{
uae_u32 *m;
addr &= a3000hmem_mask;
m = (uae_u32 *)(a3000hmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 a3000hmem_wget (uaecptr addr)
{
uae_u16 *m;
addr &= a3000hmem_mask;
m = (uae_u16 *)(a3000hmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 a3000hmem_bget (uaecptr addr)
{
addr &= a3000hmem_mask;
return a3000hmemory[addr];
}
static void REGPARAM2 a3000hmem_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= a3000hmem_mask;
m = (uae_u32 *)(a3000hmemory + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 a3000hmem_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= a3000hmem_mask;
m = (uae_u16 *)(a3000hmemory + addr);
do_put_mem_word (m, w);
}
static void REGPARAM2 a3000hmem_bput (uaecptr addr, uae_u32 b)
{
addr &= a3000hmem_mask;
a3000hmemory[addr] = b;
}
static int REGPARAM2 a3000hmem_check (uaecptr addr, uae_u32 size)
{
addr &= a3000hmem_mask;
return (addr + size) <= allocated_a3000hmem;
}
static uae_u8 *REGPARAM2 a3000hmem_xlate (uaecptr addr)
{
addr &= a3000hmem_mask;
return a3000hmemory + addr;
}
/* Kick memory */
uae_u8 *kickmemory;
uae_u16 kickstart_version;
static int kickmem_size;
/*
* A1000 kickstart RAM handling
*
* RESET instruction unhides boot ROM and disables write protection
* write access to boot ROM hides boot ROM and enables write protection
*
*/
static int a1000_kickstart_mode;
static uae_u8 *a1000_bootrom;
static void a1000_handle_kickstart (int mode)
{
if (!a1000_bootrom)
return;
if (mode == 0) {
a1000_kickstart_mode = 0;
memcpy (kickmemory, kickmemory + 262144, 262144);
kickstart_version = (kickmemory[262144 + 12] << 8) | kickmemory[262144 + 13];
} else {
a1000_kickstart_mode = 1;
memcpy (kickmemory, a1000_bootrom, 262144);
kickstart_version = 0;
}
if (kickstart_version == 0xffff)
kickstart_version = 0;
}
void a1000_reset (void)
{
a1000_handle_kickstart (1);
}
static uae_u32 REGPARAM3 kickmem_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 kickmem_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 kickmem_bget (uaecptr) REGPARAM;
static void REGPARAM3 kickmem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 kickmem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 kickmem_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 kickmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 kickmem_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM2 kickmem_lget (uaecptr addr)
{
uae_u32 *m;
addr &= kickmem_mask;
m = (uae_u32 *)(kickmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 kickmem_wget (uaecptr addr)
{
uae_u16 *m;
addr &= kickmem_mask;
m = (uae_u16 *)(kickmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 kickmem_bget (uaecptr addr)
{
addr &= kickmem_mask;
return kickmemory[addr];
}
static void REGPARAM2 kickmem_lput (uaecptr addr, uae_u32 b)
{
uae_u32 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (a1000_kickstart_mode) {
if (addr >= 0xfc0000) {
addr &= kickmem_mask;
m = (uae_u32 *)(kickmemory + addr);
do_put_mem_long (m, b);
return;
} else
a1000_handle_kickstart (0);
} else if (currprefs.illegal_mem)
write_log (L"Illegal kickmem lput at %08lx\n", addr);
}
static void REGPARAM2 kickmem_wput (uaecptr addr, uae_u32 b)
{
uae_u16 *m;
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (a1000_kickstart_mode) {
if (addr >= 0xfc0000) {
addr &= kickmem_mask;
m = (uae_u16 *)(kickmemory + addr);
do_put_mem_word (m, b);
return;
} else
a1000_handle_kickstart (0);
} else if (currprefs.illegal_mem)
write_log (L"Illegal kickmem wput at %08lx\n", addr);
}
static void REGPARAM2 kickmem_bput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
if (a1000_kickstart_mode) {