v1.2

Features

Utilized GNU FR60 cross compiler to generate ghidra p-code test suite and validate decompilation logic. Identified following issues:

• LDM Byte order reversed from SDM, not reflected in decomp - [FIXED]
• Branch instruction delay slot ordering not accurate to runtime. Branch flag read before delay slot, but delay slot still executes before branch. - [FIXED]
• Few off by one errors with ENTRY and LEAVE - [FIXED]
• DIV instructions not accurate - [TODO]

These changes allow emulating of FR60 processor code within ghidra (with the exception of the DIV instructions). The few fixes identified, especially the one around delay slots, greatly improve readability of -O3 code with large number of branches.

v1.1

Features

• Fixed byte ordering in STM0/STM1 and LDM0/LDM1

v1.0

First functional release!

Features

• Full FR60 Dissassembly and Decompilation
• Auto-Function detection, syscall identification
• DVRP Firmware auto-loader

v0.2

Full Changelog: v0.1...v0.2
Fixed stack references!

v0.1

Full Changelog: https://github.com/desrdev/ghidra-fr60/commits/v0.1