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devchadha-jmi/README.md

Hi! Dev here 👋

I am an individual with a strong technical foundation in Digital Electronics and VLSI design. I have a keen interest in RISC V, FPGAs & ASIC Design and Verification, with an experience in Verilog HDL and programming. I am open to working in different areas and doing specific tasks related to what I am studying. I am eager to contribute my skills and knowledge to the team and gain practical experience. I have excellent communication skills and a strong desire to learn and grow, making me an asset to any team..

  • 😎 Selected for the Linux Foundation's Spring 2023 Mentorship Program under RISC-V International.
  • 🌱 Currently learning: Advanced Digital Design
  • 📫 How to reach me: chadhadev2002@gmail.com

Forgive my cat please

🌐 Connect with Me

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📈 GitHub Stats & Streaks

Dev's GitHub stats Top Languages


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  1. HDL-Bits-Solutions HDL-Bits-Solutions Public

    Adding solutions of problems I have solved so far on HDLBits. Hope this helps :-)

    Verilog 3

  2. 100-Days-of-RTL 100-Days-of-RTL Public

    I started off to work on RTL Design for 100 days. Falling short with problems so decided to go ahead solving problems on HDLBits. Would continue here once I start my verification journey.

    Verilog 2

  3. Implementation-of-Quantum-Key-Distribution-protocol-BB84-on-FPGA Implementation-of-Quantum-Key-Distribution-protocol-BB84-on-FPGA Public

    This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has been designed using cryptographic protocol along with paralle…

    Verilog 4 1

  4. FIR-and-IIR-using-Verilog-and-HLS FIR-and-IIR-using-Verilog-and-HLS Public

    This repository carries the design of FIR and IIR based Low Pass Filter, designed using Verilog and HLS

    JavaScript 2 2

  5. JAMIA-RISC-V JAMIA-RISC-V Public

    JAMIA-RISC-V Core is a three stage pipelined general purpose processor written in Verilog using RV32I ISA.

    Verilog 1