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fixed mips tests
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Aysylu committed May 19, 2013
1 parent e6702ad commit 36b0c46
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Showing 2 changed files with 103 additions and 191 deletions.
179 changes: 3 additions & 176 deletions src/piplin/mips.clj
View file
Expand Up @@ -11,6 +11,7 @@
`(def ~name (enum (conj #{} ~@values))))

;; Register index
;; TODO indices are wrong for the decoder
(defenum rindx
:r0
:r1
Expand Down Expand Up @@ -119,17 +120,6 @@
schema))]
(cast instr {tag data})))

(defunion alu-result
:alu (bundle {:dst rindx :data data})
:nothing (bits 1)
)

(defn ->alu-result
([]
(cast alu-result {:nothing #b0}))
([dst data]
(cast wbresult {:alu {:dst dst :data data}})))

(let [opFUNC #b000000 fcSLL #b000000
opRT #b000001 fcSRL #b000010
opRS #b010000 fcSRA #b000011
Expand Down Expand Up @@ -313,18 +303,13 @@
(sext32 (bit-cat high-bit x))
x)))

(assert (= (sext32 #b0001) #b00000000_00000000_00000000_0000_0001))
(assert (= (sext32 #b1000) #b11111111_11111111_11111111_1111_1000))

(defn zext32
"Zero extends the input to 32 bits"
[x]
(let [width (bit-width-of (typeof x))]
(if (not= width 32)
(zext32 (bit-cat #b0 x))
x)))
(assert (= (zext32 #b0001) #b00000000_00000000_00000000_0000_0001))
(assert (= (zext32 #b1000) #b00000000_00000000_00000000_0000_1000))

(defmacro defbarrelshifter
[name docstring [x shamt] case-fn ovf-expr]
Expand All @@ -348,41 +333,6 @@
(apply bit-cat (repeat 32 (bit-slice x 31 32)))
)

;; shift by 7 without sign bit
(assert (= (sra #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b00000000_00000000_00000001_00000000))

;; shift by 7 with sign bit
(assert (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b11111111_00000000_00000001_00000000))

;; shift by 0
(assert (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000000)
#b10000000_00000000_10000000_00000000))

;; shift by 31 without sign bit
(assert (= (sra #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b00000000_00000000_00000000_00000000))

;; shift by 31 with sign bit
(assert (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b11111111_11111111_11111111_11111111))

;; shift by 32 without sign bit
(assert (= (sra #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00100000)
#b00000000_00000000_00000000_00000000))

;; shift by 32 with sign bit
(assert (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00100000)
#b11111111_11111111_11111111_11111111))

(defbarrelshifter srl
"Shift right logical"
[x shamt]
Expand All @@ -391,26 +341,6 @@
[(bit-slice x i 32)])))
(cast (bits 32) 0))

;; shift by 7
(assert (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b00000000_00000000_00000001_00000000))

;; shift by 0
(assert (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000000)
#b00000000_00000000_10000000_00000000))

;; shift by 31
(assert (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b00000000_00000000_00000000_00000000))

;; shift by 63
(assert (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00111111)
#b00000000_00000000_00000000_00000000))

(defbarrelshifter sll
"Shift left logical"
[x shamt]
Expand All @@ -421,26 +351,6 @@
)))
(cast (bits 32) 0))

;; shift by 7
(assert (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b00000000_01000000_00000000_00000000))

;; shift by 0
(assert (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000000)
#b00000000_00000000_10000000_00000000))

;; shift by 31
(assert (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b00000000_00000000_00000000_00000000))

;; shift by 63
(assert (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00111111)
#b00000000_00000000_00000000_00000000))

(defn s>
[x y]
(> (deserialize (sints 32) x) (deserialize (sints 32) y)))
Expand All @@ -454,39 +364,6 @@
[x y]
(<= (deserialize (sints 32) x) (deserialize (sints 32) y)))

(defn alu
"Does an ALU operation. Could be extended
to include reorder tag, pc predicted addr,
and prediction epoch.
This is a helper function, not a hardware function,
although its results are synthesizable, the dispatch
isn't."
[op x y rdst]
(let [->wb (partial ->wb :reg rdst)]
(case op
:+ (->wb (+ x y))
;; TODO: make sure the signed/unsigned comparison
;; of slt/sltu works
:slt (->wb (mux2 (< x y)
1 0))
:sltu (->wb (mux2 (< x y)
1 0))
:sll (->wb (bit-shift-left x y))
:srl (->wb (bit-shift-right x y))
;; TODO: srl and sra should be different
:sra (->wb (bit-shift-right x y))
:sub (->wb (- x y))
:and (->wb (bit-and x y))
:or (->wb (bit-or x y))
:xor (->wb (bit-xor x y))
:nor (->wb (bit-not (bit-or x y)))
:lui (->wb (bit-cat (bit-slice x 0 16)
(cast (bits 16) 0)))
)
)
)

(def alu-op
(bundle {:op (:enum instr)
:pc addr
Expand Down Expand Up @@ -522,7 +399,7 @@
(cast alu-or-store-op
{:store {:pc pc :addr addr :data data}}))

(defn resolve
(defn resolve-operands
"Takes a decoded instr, the pc, and the regfile
and resolves the operands, returning either
a store or an alu op."
Expand Down Expand Up @@ -616,7 +493,7 @@
(->alu-op :add pc (cast data 0) (cast data 0) (cast rindx 0)))))

(def reg-writeback
(bundle {:pc data
(bundle {:pc addr
:dst rindx
:val data}))

Expand Down Expand Up @@ -675,53 +552,3 @@
:bgez (->writeback (mux2 (s> x y)
pc+4
pc+imm) :r0 0))))))

#_(defn evaluate
"Takes an instr, a regfile, and a memory, and returns the result."
[instr regfile memory]
(letfn [(sreg [rindx] (->signed (regfile rindx)))
(zreg [rindx] (->unsigned (regfile rindx)))]
(union-match
instr
;; Memory operations
(:lw {:keys [rbase rdst offset]}
(->wb :reg
rdst
(get memory (+ (sreg rbase)
(sext32 offset)))))
(:sw {:keys [rbase rsrc offset]}
(->wb :mem
(+ (sreg rbase)
(sext32 offset))
(regfile rsrc)))

(:addiu {:keys [rsrc rdst imm]}
(alu :+ (sreg rsrc) (sext32 imm) rdst))
(:stli {:keys [rsrc rdst imm]}
(->wb :reg
rdst
(mux2 (< (sreg rsrc) (sext32 imm))
1 0)))
(:stliu {:keys [rsrc rdst imm]}
(->wb :reg
rdst
(mux2 (< (zreg rsrc) (zext32 imm))
1 0)))
(:andi {:keys [rsrc rdst imm]}
(->wb :reg
rdst
(bit-and (zreg rsrc) (zext32 imm))))
(:ori {:keys [rsrc rdst imm]}
(->wb :reg
rdst
(bit-or (zreg rsrc) (zext32 imm))))
(:xori {:keys [rsrc rdst imm]}
(->wb :reg
rdst
(bit-xor (zreg rsrc) (zext32 imm))))
(:lui {:keys [rdst imm]}
(->wb :reg
rdst
(bit-cat imm (cast (bits 16) 0))))
))
)
115 changes: 100 additions & 15 deletions test/piplin/test/mips.clj
View file
@@ -1,19 +1,104 @@
(ns piplin.test.mips
(:use [piplin.types
[binops :only [=]]])
(:refer-clojure :as clj :exclude [not= bit-or bit-xor + - * bit-and inc dec bit-not < > <= >= = cast not cond condp and or bit-shift-right bit-shift-left pos? neg? zero?])
(:use piplin.core)
(:use [piplin.mips])
(:use [clojure.test])
(:refer-clojure :as clj :exclude [=]))
(:use [piplin.types.union :only [get-tag get-value]])
(:use [clojure.test]))

(deftest decode-add-imm
(let [decoded (decode #b001001_00001_00010_1000_0000_0000_0000)]
(is (= (get decoded :op)
(alu-op :add)))
(is (= (get decoded :y)
(reg-or-imm
{:imm (u32m 32768)})))
(is (= (get decoded :x)
(reg-or-imm
{:reg (reg :23)})))
(is (= (get decoded :dst)
(reg :22)))))
(let [decoded (decode #b001001_00001_00010_1000_0000_0000_0000)
add (get-value :addiu decoded)]
(is (= (get-tag decoded)
:addiu))
(is (= (get add :imm)
(cast simm 32768)))
(is (= (get add :rsrc)
:r17))
(is (= (get add :rdst)
:r15))))

(deftest sext-test
(is (= (sext32 #b0001) #b00000000_00000000_00000000_0000_0001))
(is (= (sext32 #b1000) #b11111111_11111111_11111111_1111_1000)))

(deftest zext-test
(is (= (zext32 #b0001) #b00000000_00000000_00000000_0000_0001))
(is (= (zext32 #b1000) #b00000000_00000000_00000000_0000_1000)))

(deftest sra-test
;; shift by 7 without sign bit
(is (= (sra #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b00000000_00000000_00000001_00000000))

;; shift by 7 with sign bit
(is (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b11111111_00000000_00000001_00000000))

;; shift by 0
(is (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000000)
#b10000000_00000000_10000000_00000000))

;; shift by 31 without sign bit
(is (= (sra #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b00000000_00000000_00000000_00000000))

;; shift by 31 with sign bit
(is (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b11111111_11111111_11111111_11111111))

;; shift by 32 without sign bit
(is (= (sra #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00100000)
#b00000000_00000000_00000000_00000000))

;; shift by 32 with sign bit
(is (= (sra #b10000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00100000)
#b11111111_11111111_11111111_11111111)))

(deftest srl-test
;; shift by 7
(is (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b00000000_00000000_00000001_00000000))

;; shift by 0
(is (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000000)
#b00000000_00000000_10000000_00000000))

;; shift by 31
(is (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b00000000_00000000_00000000_00000000))

;; shift by 63
(is (= (srl #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00111111)
#b00000000_00000000_00000000_00000000)))

(deftest sll-test
;; shift by 7
(is (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000111)
#b00000000_01000000_00000000_00000000))

;; shift by 0
(is (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00000000)
#b00000000_00000000_10000000_00000000))

;; shift by 31
(is (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00011111)
#b00000000_00000000_00000000_00000000))

;; shift by 63
(is (= (sll #b00000000_00000000_10000000_00000000
#b00000000_00000000_00000000_00111111)
#b00000000_00000000_00000000_00000000)))

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