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Nested module synthesis must use wires instead of dot notation #54

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dgrnbrg opened this issue Jan 27, 2013 · 0 comments
Closed

Nested module synthesis must use wires instead of dot notation #54

dgrnbrg opened this issue Jan 27, 2013 · 0 comments

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@dgrnbrg
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dgrnbrg commented Jan 27, 2013

Currently, we're synthesizing dot-notation to signals inside of modules, and although the simulators find this just fine, the synthesizer wants all connections to be done with wires and port connections in the module declaration.
@dgrnbrg dgrnbrg closed this as completed Jan 27, 2013
dgrnbrg added a commit that referenced this issue Feb 11, 2013
@dgrnbrg
Force all subports to be attached to wires
736d6a5 
This resolves issue #54
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