Merge branch 'master' of github.com:dgsmith/Verilog-Simulator

gatesim.cpp

@@ -1,12 +1,18 @@
+/**
+* PA5 Part 1
+* Chris Li, Grayson Smith
+*/
 #include "global.h"
 #include <iostream>
 #include "parser.h"
 
 int main (int argc, char const *argv[])
 {
-  LOG("Hi");
+  LOG("Parsing and dumping test.v");
 	Design *aDesign;
-	aDesign = parseThatShit("test2.v");
-  LOG("BYE");
+	aDesign = parseThatShit("test.v");
+
+  LOG("Parsing and dumping test2.v");
+  aDesign = parseThatShit("test2.v");
   return 0;
 }

parser.cpp

@@ -10,9 +10,12 @@ Design *parseThatShit(string ifilename)
 	//vector<string> wires;
 	vector<string> gate;
 
+  unsigned int lineNum = 0;
 	ifstream ifile(ifilename.c_str(), ifstream::in);
 	while(ifile.good())
 	{
+    lineNum++;
+
 		string currentline;
 		getline(ifile, currentline);
 		stringstream ss(currentline);