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Merge pull request #567 from diffblue/verilog-expressions-tests
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Verilog: consolidate expression-related tests in verilog/expressions
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kroening committed Jun 21, 2024
2 parents 6379de4 + 4bbab28 commit 95d47f4
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CORE
main.v
constants1.v
--bound 1
^EXIT=0$
^SIGNAL=0$
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CORE
main.v
shr1.v
--bound 1
^EXIT=0$
^SIGNAL=0$
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