Verilog: little_endian -> big_endian #584
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Verilog vectors may use indices that either increase or decrease with the significance of the indexed bit. The default is to increase, i.e., a bit with a bigger index has a higher significance.
This flips the type annotation used to distinguish the two cases from
ID_C_little_endian
, to signal the increasing case, toID_C_big_endian
.The benefit is that the common default does not require any annotation.