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README
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DSLogic-hdl is an Open-source hdl design for spartan-6 FPGA of DSLogic
DSLogic project: www.dreamsourcelab.com


Dimitar Penev, March 2015 dpn@switchvoice.com
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-Synthesis from a command line using gmake
-Added Run Length Encoding (RLE)
-Test bench using Icarus Verilog. CPU interface is not fully tested


Status
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DSLogic-hdl is in a usable state and has had official
tarball releases.


Copyright and license
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DSLogic-hdl is licensed under the terms of the GNU General Public
License (GPL), version 2 or later.


Website
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 http://www.dreamsourcelab.com