This is mainly a simulation library of xilinx primitives that are verilator compatible.
Verilog
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.gitignore
BUFG.v
BUFGMUX.v
BUFIO2.v
BUFPLL.v
DCM_SP.v
FD.v
FDC.v
FDE.v
FDP.v
FDR.v
FDRE.v
FDS.v
FDSE.v
GND.v
IBUFDS.v
IBUFGDS.v
IDDR2.v
INV.v
IOBUF.v
IODELAY2.v
ISERDES2.v
LDC.v
LUT1.v
LUT2.v
LUT3.v
LUT4.v
LUT5.v
LUT6.v
LUT6_2.v
MULT_AND.v
MUXCY.v
MUXCY_L.v
MUXF5.v
MUXF6.v
MUXF7.v
OBUFDS.v
ODDR2.v
OSERDES2.v
PLL_BASE.v
RAM16X1D.v
RAM32X1D.v
RAMB16BWER.v
README
SRL16E.v
VCC.v
XORCY.v

README

This is mainly a simulation library of xilinx primitives that are
verilator compatible.