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This is mainly a simulation library of xilinx primitives that are verilator compatible.
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.gitignore | ||
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BUFG.v | ||
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BUFGMUX.v | ||
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BUFIO2.v | ||
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BUFPLL.v | ||
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DCM_SP.v | ||
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FD.v | ||
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FDC.v | ||
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FDE.v | ||
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FDP.v | ||
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FDR.v | ||
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FDRE.v | ||
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FDS.v | ||
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FDSE.v | ||
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GND.v | ||
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IBUFDS.v | ||
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IBUFGDS.v | ||
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IDDR2.v | ||
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INV.v | ||
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IOBUF.v | ||
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IODELAY2.v | ||
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ISERDES2.v | ||
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LDC.v | ||
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LUT1.v | ||
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LUT2.v | ||
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LUT3.v | ||
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LUT4.v | ||
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LUT5.v | ||
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LUT6.v | ||
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LUT6_2.v | ||
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MULT_AND.v | ||
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MUXCY.v | ||
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MUXCY_L.v | ||
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MUXF5.v | ||
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MUXF6.v | ||
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MUXF7.v | ||
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OBUFDS.v | ||
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ODDR2.v | ||
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OSERDES2.v | ||
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PLL_BASE.v | ||
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RAM16X1D.v | ||
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RAM32X1D.v | ||
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RAMB16BWER.v | ||
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README | ||
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SRL16E.v | ||
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VCC.v | ||
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XORCY.v | ||
README
This is mainly a simulation library of xilinx primitives that are verilator compatible.