Add proper frequency control

[jeanthom]

Maybe it is time to fix one of the earliest issues of DirtyJTAG, issue #13

[jeanthom]

This PR shows promising results but there are some bugs:

master output:

IR length: 8
Chain length: 1
Device Id: 01001001011000000010000010010011 (0x49602093)
  Manufacturer: Xilinx (0x093)
  Part(0):      xc9536xl (0x9602)
  Stepping:     4
  Filename:     /usr/share/urjtag/xilinx/xc9536xl/xc9536xl_cs48

jtag-freq output:

IR length: 9
Chain length: 2
Device Id: 01001001011000000010000010010011 (0x49602093)
  Manufacturer: Xilinx (0x093)
  Part(0):      xc9536xl (0x9602)
  Stepping:     4
  Filename:     /usr/share/urjtag/xilinx/xc9536xl/xc9536xl_cs48
Device Id: not supported (bit 0 was not a 1)

[jeanthom]

I've captured both signals using Sigrok:

• D0: TMS
• D1: TDI
• D2: TDO
• D3: TCK

capture.zip

[jeanthom]

Looks like TDI comes right after TCK which introduces some delay. Will try to swap jtag_set_tck and jtag_set_tdi calls in tim2_isr.

[jeanthom]

Reversing the function order seems to solve the issue but I'm worried by the delay between TCK and TDI. Perhaps direct write to the registers could trim the fat?

[jeanthom]

The narrator: writing directly to the registers did improve the latency between TDI and TCK signals, making Jean the happiest child on earth...

[jeanthom]

Uniport (write once to the port register for TDI/TCK) functionality was removed as it turned out to be unreliable.

jtag-freq works great on Blue Pill target, we can get faster than the 50kHz we used to have.