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real_time_tester_hw.tcl
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real_time_tester_hw.tcl
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# TCL File Generated by Component Editor 14.0
# Sun Feb 01 14:10:48 CET 2015
# DO NOT MODIFY
#
# real_time_tester "real_time_tester" v2.0
# Kyrre Gonsholt 2015.02.01.14:10:48
# Real-time tester
#
#
# request TCL package from ACDS 14.0
#
package require -exact qsys 14.0
#
# module real_time_tester
#
set_module_property DESCRIPTION "Real-time tester"
set_module_property NAME real_time_tester
set_module_property VERSION 2.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Real-time tester"
set_module_property AUTHOR "Kyrre Gonsholt"
set_module_property DISPLAY_NAME real_time_tester
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL custom_module
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file custom_module.v VERILOG PATH ../custom_module/src/custom_module.v TOP_LEVEL_FILE
add_fileset_file avalonMM_master.v VERILOG PATH ../custom_module/src/avalonMM_master.v
add_fileset_file clock_crossing.v VERILOG PATH ../custom_module/src/clock_crossing.v
add_fileset_file RTS_tester.v VERILOG PATH ../custom_module/src/RTS_tester.v
add_fileset_file altera_fifo_ip.v VERILOG PATH ../custom_module/src/ip/altera_fifo_ip.v
add_fileset_file defines.vh OTHER PATH ../custom_module/src/defines.vh
#
# parameters
#
add_parameter M0_DATA_WIDTH INTEGER 64
set_parameter_property M0_DATA_WIDTH DEFAULT_VALUE 64
set_parameter_property M0_DATA_WIDTH DISPLAY_NAME M0_DATA_WIDTH
set_parameter_property M0_DATA_WIDTH TYPE INTEGER
set_parameter_property M0_DATA_WIDTH UNITS None
set_parameter_property M0_DATA_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property M0_DATA_WIDTH HDL_PARAMETER true
add_parameter M0_ADDR_WIDTH INTEGER 32
set_parameter_property M0_ADDR_WIDTH DEFAULT_VALUE 32
set_parameter_property M0_ADDR_WIDTH DISPLAY_NAME M0_ADDR_WIDTH
set_parameter_property M0_ADDR_WIDTH TYPE INTEGER
set_parameter_property M0_ADDR_WIDTH UNITS None
set_parameter_property M0_ADDR_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property M0_ADDR_WIDTH HDL_PARAMETER true
add_parameter M0_BURST_START INTEGER 8
set_parameter_property M0_BURST_START DEFAULT_VALUE 8
set_parameter_property M0_BURST_START DISPLAY_NAME M0_BURST_START
set_parameter_property M0_BURST_START TYPE INTEGER
set_parameter_property M0_BURST_START UNITS None
set_parameter_property M0_BURST_START ALLOWED_RANGES -2147483648:2147483647
set_parameter_property M0_BURST_START HDL_PARAMETER true
add_parameter M0_BURST_START_REG_WIDTH INTEGER 4
set_parameter_property M0_BURST_START_REG_WIDTH DEFAULT_VALUE 4
set_parameter_property M0_BURST_START_REG_WIDTH DISPLAY_NAME M0_BURST_START_REG_WIDTH
set_parameter_property M0_BURST_START_REG_WIDTH TYPE INTEGER
set_parameter_property M0_BURST_START_REG_WIDTH UNITS None
set_parameter_property M0_BURST_START_REG_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property M0_BURST_START_REG_WIDTH HDL_PARAMETER true
#
# module assignments
#
set_module_assignment embeddedsw.dts.compatible real_time_tester
set_module_assignment embeddedsw.dts.group real_time_tester
set_module_assignment embeddedsw.dts.vendor keag
#
# display items
#
#
# connection point s0
#
add_interface s0 avalon end
set_interface_property s0 addressUnits SYMBOLS
set_interface_property s0 associatedClock clock
set_interface_property s0 associatedReset reset
set_interface_property s0 bitsPerSymbol 8
set_interface_property s0 burstOnBurstBoundariesOnly false
set_interface_property s0 burstcountUnits WORDS
set_interface_property s0 explicitAddressSpan 64
set_interface_property s0 holdTime 0
set_interface_property s0 linewrapBursts false
set_interface_property s0 maximumPendingReadTransactions 0
set_interface_property s0 maximumPendingWriteTransactions 0
set_interface_property s0 readLatency 0
set_interface_property s0 readWaitStates 0
set_interface_property s0 readWaitTime 0
set_interface_property s0 setupTime 0
set_interface_property s0 timingUnits Cycles
set_interface_property s0 writeWaitTime 0
set_interface_property s0 ENABLED true
set_interface_property s0 EXPORT_OF ""
set_interface_property s0 PORT_NAME_MAP ""
set_interface_property s0 CMSIS_SVD_VARIABLES ""
set_interface_property s0 SVD_ADDRESS_GROUP ""
add_interface_port s0 avs_s0_address address Input 8
add_interface_port s0 avs_s0_read read Input 1
add_interface_port s0 avs_s0_readdata readdata Output 32
add_interface_port s0 avs_s0_write write Input 1
add_interface_port s0 avs_s0_writedata writedata Input 32
set_interface_assignment s0 embeddedsw.configuration.isFlash 0
set_interface_assignment s0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment s0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment s0 embeddedsw.configuration.isPrintableDevice 0
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset_n reset_n Input 1
#
# connection point m0
#
add_interface m0 avalon start
set_interface_property m0 addressUnits SYMBOLS
set_interface_property m0 associatedClock clock
set_interface_property m0 associatedReset reset
set_interface_property m0 bitsPerSymbol 8
set_interface_property m0 burstOnBurstBoundariesOnly false
set_interface_property m0 burstcountUnits WORDS
set_interface_property m0 doStreamReads false
set_interface_property m0 doStreamWrites false
set_interface_property m0 holdTime 0
set_interface_property m0 linewrapBursts false
set_interface_property m0 maximumPendingReadTransactions 0
set_interface_property m0 maximumPendingWriteTransactions 0
set_interface_property m0 readLatency 0
set_interface_property m0 readWaitTime 1
set_interface_property m0 setupTime 0
set_interface_property m0 timingUnits Cycles
set_interface_property m0 writeWaitTime 0
set_interface_property m0 ENABLED true
set_interface_property m0 EXPORT_OF ""
set_interface_property m0 PORT_NAME_MAP ""
set_interface_property m0 CMSIS_SVD_VARIABLES ""
set_interface_property m0 SVD_ADDRESS_GROUP ""
add_interface_port m0 avm_m0_address address Output 32
add_interface_port m0 avm_m0_write write Output 1
add_interface_port m0 avm_m0_writedata writedata Output M0_DATA_WIDTH
add_interface_port m0 avm_m0_waitrequest waitrequest Input 1
add_interface_port m0 avm_m0_burstcount burstcount Output 4
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock
set_interface_property conduit_end associatedReset reset
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end signal_ack ack Input 4
add_interface_port conduit_end signal_R_Wn r_wn Input 1
add_interface_port conduit_end signal_int int Output 4
add_interface_port conduit_end packet_id data Bidir 7