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cod2.d
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cod2.d
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/**
* Compiler implementation of the
* $(LINK2 http://www.dlang.org, D programming language).
*
* Copyright: Copyright (C) 1984-1998 by Symantec
* Copyright (C) 2000-2020 by The D Language Foundation, All Rights Reserved
* Authors: $(LINK2 http://www.digitalmars.com, Walter Bright)
* License: $(LINK2 http://www.boost.org/LICENSE_1_0.txt, Boost License 1.0)
* Source: $(LINK2 https://github.com/dlang/dmd/blob/master/src/dmd/backend/cod2.d, backend/cod2.d)
* Coverage: https://codecov.io/gh/dlang/dmd/src/master/src/dmd/backend/cod2.d
*/
module dmd.backend.cod2;
version (SCPP)
version = COMPILE;
version (MARS)
version = COMPILE;
version (COMPILE)
{
import core.stdc.stdio;
import core.stdc.stdlib;
import core.stdc.string;
import dmd.backend.backend;
import dmd.backend.cc;
import dmd.backend.cdef;
import dmd.backend.code;
import dmd.backend.code_x86;
import dmd.backend.codebuilder;
import dmd.backend.mem;
import dmd.backend.el;
import dmd.backend.exh;
import dmd.backend.global;
import dmd.backend.oper;
import dmd.backend.ty;
import dmd.backend.type;
import dmd.backend.xmm;
extern (C++):
nothrow:
int REGSIZE();
extern __gshared CGstate cgstate;
extern __gshared ubyte[FLMAX] segfl;
extern __gshared bool[FLMAX] stackfl;
__gshared int cdcmp_flag;
private extern (D) uint mask(uint m) { return 1 << m; }
// from divcoeff.c
extern (C)
{
bool choose_multiplier(int N, ulong d, int prec, ulong *pm, int *pshpost);
bool udiv_coefficients(int N, ulong d, int *pshpre, ulong *pm, int *pshpost);
}
/*******************************
* Swap two registers.
*/
private void swap(reg_t *a,reg_t *b)
{
const tmp = *a;
*a = *b;
*b = tmp;
}
/*******************************************
* Returns: true if cannot use this EA in anything other than a MOV instruction.
*/
bool movOnly(const elem *e)
{
if (config.exe & EX_OSX64 && config.flags3 & CFG3pic && e.Eoper == OPvar)
{
const s = e.EV.Vsym;
// Fixups for these can only be done with a MOV
if (s.Sclass == SCglobal || s.Sclass == SCextern ||
s.Sclass == SCcomdat || s.Sclass == SCcomdef)
return true;
}
return false;
}
/********************************
* Determine index registers used by addressing mode.
* Index is rm of modregrm field.
* Returns:
* mask of index registers
*/
regm_t idxregm(const code* c)
{
const rm = c.Irm;
regm_t idxm;
if ((rm & 0xC0) != 0xC0) /* if register is not the destination */
{
if (I16)
{
static immutable ubyte[8] idxrm = [mBX|mSI,mBX|mDI,mSI,mDI,mSI,mDI,0,mBX];
idxm = idxrm[rm & 7];
}
else
{
if ((rm & 7) == 4) /* if sib byte */
{
const sib = c.Isib;
reg_t idxreg = (sib >> 3) & 7;
// scaled index reg
idxm = mask(idxreg | ((c.Irex & REX_X) ? 8 : 0));
if ((sib & 7) == 5 && (rm & 0xC0) == 0)
{ }
else
idxm |= mask((sib & 7) | ((c.Irex & REX_B) ? 8 : 0));
}
else
idxm = mask((rm & 7) | ((c.Irex & REX_B) ? 8 : 0));
}
}
return idxm;
}
static if (TARGET_WINDOS)
{
/***************************
* Gen code for call to floating point routine.
*/
void opdouble(ref CodeBuilder cdb, elem *e,regm_t *pretregs,uint clib)
{
if (config.inline8087)
{
orth87(cdb,e,pretregs);
return;
}
regm_t retregs1,retregs2;
if (tybasic(e.EV.E1.Ety) == TYfloat)
{
clib += CLIB.fadd - CLIB.dadd; /* convert to float operation */
retregs1 = FLOATREGS;
retregs2 = FLOATREGS2;
}
else
{
if (I32)
{ retregs1 = DOUBLEREGS_32;
retregs2 = DOUBLEREGS2_32;
}
else
{ retregs1 = mSTACK;
retregs2 = DOUBLEREGS_16;
}
}
codelem(cdb,e.EV.E1, &retregs1,false);
if (retregs1 & mSTACK)
cgstate.stackclean++;
scodelem(cdb,e.EV.E2, &retregs2, retregs1 & ~mSTACK, false);
if (retregs1 & mSTACK)
cgstate.stackclean--;
callclib(cdb, e, clib, pretregs, 0);
}
}
/*****************************
* Handle operators which are more or less orthogonal
* ( + - & | ^ )
*/
void cdorth(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
//printf("cdorth(e = %p, *pretregs = %s)\n",e,regm_str(*pretregs));
elem *e1 = e.EV.E1;
elem *e2 = e.EV.E2;
if (*pretregs == 0) // if don't want result
{
codelem(cdb,e1,pretregs,false); // eval left leaf
*pretregs = 0; // in case they got set
codelem(cdb,e2,pretregs,false);
return;
}
const ty = tybasic(e.Ety);
const ty1 = tybasic(e1.Ety);
if (tyfloating(ty1))
{
if (tyvector(ty1) ||
config.fpxmmregs && tyxmmreg(ty1) &&
!(*pretregs & mST0) &&
!(*pretregs & mST01) &&
!(ty == TYldouble || ty == TYildouble) // watch out for shrinkLongDoubleConstantIfPossible()
)
{
orthxmm(cdb,e,pretregs);
return;
}
if (config.inline8087)
{
orth87(cdb,e,pretregs);
return;
}
static if (TARGET_WINDOS)
{
opdouble(cdb,e,pretregs,(e.Eoper == OPadd) ? CLIB.dadd
: CLIB.dsub);
return;
}
else
{
assert(0);
}
}
if (tyxmmreg(ty1))
{
orthxmm(cdb,e,pretregs);
return;
}
opcode_t op1, op2;
uint mode;
__gshared int nest;
const ty2 = tybasic(e2.Ety);
const e2oper = e2.Eoper;
const sz = _tysize[ty];
const isbyte = (sz == 1);
code_flags_t word = (!I16 && sz == SHORTSIZE) ? CFopsize : 0;
bool test = false; // assume we destroyed lvalue
switch (e.Eoper)
{
case OPadd: mode = 0;
op1 = 0x03; op2 = 0x13; break; /* ADD, ADC */
case OPmin: mode = 5;
op1 = 0x2B; op2 = 0x1B; break; /* SUB, SBB */
case OPor: mode = 1;
op1 = 0x0B; op2 = 0x0B; break; /* OR , OR */
case OPxor: mode = 6;
op1 = 0x33; op2 = 0x33; break; /* XOR, XOR */
case OPand: mode = 4;
op1 = 0x23; op2 = 0x23; /* AND, AND */
if (tyreg(ty1) &&
*pretregs == mPSW) /* if flags only */
{
test = true;
op1 = 0x85; /* TEST */
mode = 0;
}
break;
default:
assert(0);
}
op1 ^= isbyte; /* if byte operation */
// Compute numwords, the number of words to operate on.
int numwords = 1;
if (!I16)
{
/* Cannot operate on longs and then do a 'paint' to a far */
/* pointer, because far pointers are 48 bits and longs are 32. */
/* Therefore, numwords can never be 2. */
assert(!(tyfv(ty1) && tyfv(ty2)));
if (sz == 2 * REGSIZE)
{
numwords++;
}
}
else
{
/* If ty is a TYfptr, but both operands are long, treat the */
/* operation as a long. */
if ((tylong(ty1) || ty1 == TYhptr) &&
(tylong(ty2) || ty2 == TYhptr))
numwords++;
}
// Special cases where only flags are set
if (test && _tysize[ty1] <= REGSIZE &&
(e1.Eoper == OPvar || (e1.Eoper == OPind && !e1.Ecount))
&& !movOnly(e1)
)
{
// Handle the case of (var & const)
if (e2.Eoper == OPconst && el_signx32(e2))
{
code cs = void;
cs.Iflags = 0;
cs.Irex = 0;
getlvalue(cdb,&cs,e1,0);
targ_size_t value = e2.EV.Vpointer;
if (sz == 2)
value &= 0xFFFF;
else if (sz == 4)
value &= 0xFFFFFFFF;
reg_t reg;
if (reghasvalue(isbyte ? BYTEREGS : ALLREGS,value,®))
{
code_newreg(&cs, reg);
if (I64 && isbyte && reg >= 4)
cs.Irex |= REX;
}
else
{
if (sz == 8 && !I64)
{
assert(value == cast(int)value); // sign extend imm32
}
op1 = 0xF7;
cs.IEV2.Vint = cast(targ_int)value;
cs.IFL2 = FLconst;
}
cs.Iop = op1 ^ isbyte;
cs.Iflags |= word | CFpsw;
freenode(e1);
freenode(e2);
cdb.gen(&cs);
return;
}
// Handle (exp & reg)
reg_t reg;
regm_t retregs;
if (isregvar(e2,&retregs,®))
{
code cs = void;
cs.Iflags = 0;
cs.Irex = 0;
getlvalue(cdb,&cs,e1,0);
code_newreg(&cs, reg);
if (I64 && isbyte && reg >= 4)
cs.Irex |= REX;
cs.Iop = op1 ^ isbyte;
cs.Iflags |= word | CFpsw;
freenode(e1);
freenode(e2);
cdb.gen(&cs);
return;
}
}
code cs = void;
cs.Iflags = 0;
cs.Irex = 0;
// Look for possible uses of LEA
if (e.Eoper == OPadd &&
!(*pretregs & mPSW) && // flags aren't set by LEA
!nest && // could cause infinite recursion if e.Ecount
(sz == REGSIZE || (I64 && sz == 4))) // far pointers aren't handled
{
const rex = (sz == 8) ? REX_W : 0;
// Handle the case of (e + &var)
int e1oper = e1.Eoper;
if ((e2oper == OPrelconst && (config.target_cpu >= TARGET_Pentium || (!e2.Ecount && stackfl[el_fl(e2)])))
|| // LEA costs too much for simple EAs on older CPUs
(e2oper == OPconst && (e1.Eoper == OPcall || e1.Eoper == OPcallns) && !(*pretregs & mAX)) ||
(!I16 && (isscaledindex(e1) || isscaledindex(e2))) ||
(!I16 && e1oper == OPvar && e1.EV.Vsym.Sfl == FLreg && (e2oper == OPconst || (e2oper == OPvar && e2.EV.Vsym.Sfl == FLreg))) ||
(e2oper == OPconst && e1oper == OPeq && e1.EV.E1.Eoper == OPvar) ||
(!I16 && (e2oper == OPrelconst || e2oper == OPconst) && !e1.Ecount &&
(e1oper == OPmul || e1oper == OPshl) &&
e1.EV.E2.Eoper == OPconst &&
ssindex(e1oper,e1.EV.E2.EV.Vuns)
) ||
(!I16 && e1.Ecount)
)
{
const inc = e.Ecount != 0;
nest += inc;
code csx = void;
getlvalue(cdb,&csx,e,0);
nest -= inc;
reg_t regx;
allocreg(cdb,pretregs,®x,ty);
csx.Iop = LEA;
code_newreg(&csx, regx);
cdb.gen(&csx); // LEA regx,EA
if (rex)
code_orrex(cdb.last(), rex);
return;
}
// Handle the case of ((e + c) + e2)
if (!I16 &&
e1oper == OPadd &&
(e1.EV.E2.Eoper == OPconst && el_signx32(e1.EV.E2) ||
e2oper == OPconst && el_signx32(e2)) &&
!e1.Ecount
)
{
elem *ebase;
elem *edisp;
if (e2oper == OPconst && el_signx32(e2))
{ edisp = e2;
ebase = e1.EV.E2;
}
else
{ edisp = e1.EV.E2;
ebase = e2;
}
auto e11 = e1.EV.E1;
regm_t retregs = *pretregs & ALLREGS;
if (!retregs)
retregs = ALLREGS;
int ss = 0;
int ss2 = 0;
// Handle the case of (((e * c1) + c2) + e2)
// Handle the case of (((e << c1) + c2) + e2)
if ((e11.Eoper == OPmul || e11.Eoper == OPshl) &&
e11.EV.E2.Eoper == OPconst &&
!e11.Ecount
)
{
const co1 = cast(targ_size_t)el_tolong(e11.EV.E2);
if (e11.Eoper == OPshl)
{
if (co1 > 3)
goto L13;
ss = cast(int)co1;
}
else
{
ss2 = 1;
switch (co1)
{
case 6: ss = 1; break;
case 12: ss = 1; ss2 = 2; break;
case 24: ss = 1; ss2 = 3; break;
case 10: ss = 2; break;
case 20: ss = 2; ss2 = 2; break;
case 40: ss = 2; ss2 = 3; break;
case 18: ss = 3; break;
case 36: ss = 3; ss2 = 2; break;
case 72: ss = 3; ss2 = 3; break;
default:
ss2 = 0;
goto L13;
}
}
freenode(e11.EV.E2);
freenode(e11);
e11 = e11.EV.E1;
L13:
{ }
}
reg_t reg11;
regm_t regm;
if (e11.Eoper == OPvar && isregvar(e11,®m,®11))
{
if (tysize(e11.Ety) <= REGSIZE)
retregs = mask(reg11); // only want the LSW
else
retregs = regm;
freenode(e11);
}
else
codelem(cdb,e11,&retregs,false);
regm_t rretregs = ALLREGS & ~retregs & ~mBP;
scodelem(cdb,ebase,&rretregs,retregs,true);
reg_t reg;
{
regm_t sregs = *pretregs & ~rretregs;
if (!sregs)
sregs = ALLREGS & ~rretregs;
allocreg(cdb,&sregs,®,ty);
}
assert((retregs & (retregs - 1)) == 0); // must be only one register
assert((rretregs & (rretregs - 1)) == 0); // must be only one register
auto reg1 = findreg(retregs);
const reg2 = findreg(rretregs);
if (ss2)
{
assert(reg != reg2);
if ((reg1 & 7) == BP)
{ static immutable uint[4] imm32 = [1+1,2+1,4+1,8+1];
// IMUL reg,imm32
cdb.genc2(0x69,modregxrmx(3,reg,reg1),imm32[ss]);
}
else
{ // LEA reg,[reg1*ss][reg1]
cdb.gen2sib(LEA,modregxrm(0,reg,4),modregrm(ss,reg1 & 7,reg1 & 7));
if (reg1 & 8)
code_orrex(cdb.last(), REX_X | REX_B);
}
if (rex)
code_orrex(cdb.last(), rex);
reg1 = reg;
ss = ss2; // use *2 for scale
}
cs.Iop = LEA; // LEA reg,c[reg1*ss][reg2]
cs.Irm = modregrm(2,reg & 7,4);
cs.Isib = modregrm(ss,reg1 & 7,reg2 & 7);
assert(reg2 != BP);
cs.Iflags = CFoff;
cs.Irex = cast(ubyte)rex;
if (reg & 8)
cs.Irex |= REX_R;
if (reg1 & 8)
cs.Irex |= REX_X;
if (reg2 & 8)
cs.Irex |= REX_B;
cs.IFL1 = FLconst;
cs.IEV1.Vsize_t = edisp.EV.Vuns;
freenode(edisp);
freenode(e1);
cdb.gen(&cs);
fixresult(cdb,e,mask(reg),pretregs);
return;
}
}
regm_t posregs = (isbyte) ? BYTEREGS : (mES | ALLREGS | mBP);
regm_t retregs = *pretregs & posregs;
if (retregs == 0) /* if no return regs speced */
/* (like if wanted flags only) */
retregs = ALLREGS & posregs; // give us some
if (ty1 == TYhptr || ty2 == TYhptr)
{ /* Generate code for add/subtract of huge pointers.
No attempt is made to generate very good code.
*/
retregs = (retregs & mLSW) | mDX;
regm_t rretregs;
if (ty1 == TYhptr)
{ // hptr +- long
rretregs = mLSW & ~(retregs | regcon.mvar);
if (!rretregs)
rretregs = mLSW;
rretregs |= mCX;
codelem(cdb,e1,&rretregs,0);
retregs &= ~rretregs;
if (!(retregs & mLSW))
retregs |= mLSW & ~rretregs;
scodelem(cdb,e2,&retregs,rretregs,true);
}
else
{ // long + hptr
codelem(cdb,e1,&retregs,0);
rretregs = (mLSW | mCX) & ~retregs;
if (!(rretregs & mLSW))
rretregs |= mLSW;
scodelem(cdb,e2,&rretregs,retregs,true);
}
getregs(cdb,rretregs | retregs);
const mreg = DX;
const lreg = findreglsw(retregs);
if (e.Eoper == OPmin)
{ // negate retregs
cdb.gen2(0xF7,modregrm(3,3,mreg)); // NEG mreg
cdb.gen2(0xF7,modregrm(3,3,lreg)); // NEG lreg
code_orflag(cdb.last(),CFpsw);
cdb.genc2(0x81,modregrm(3,3,mreg),0); // SBB mreg,0
}
const lrreg = findreglsw(rretregs);
genregs(cdb,0x03,lreg,lrreg); // ADD lreg,lrreg
code_orflag(cdb.last(),CFpsw);
genmovreg(cdb,lrreg,CX); // MOV lrreg,CX
cdb.genc2(0x81,modregrm(3,2,mreg),0); // ADC mreg,0
genshift(cdb); // MOV CX,offset __AHSHIFT
cdb.gen2(0xD3,modregrm(3,4,mreg)); // SHL mreg,CL
genregs(cdb,0x03,mreg,lrreg); // ADD mreg,MSREG(h)
fixresult(cdb,e,retregs,pretregs);
return;
}
regm_t rretregs;
reg_t reg;
if (_tysize[ty1] > REGSIZE && numwords == 1)
{ /* The only possibilities are (TYfptr + tyword) or (TYfptr - tyword) */
debug
if (_tysize[ty2] != REGSIZE)
{
printf("e = %p, e.Eoper = ",e);
WROP(e.Eoper);
printf(" e1.Ety = ");
WRTYxx(ty1);
printf(" e2.Ety = ");
WRTYxx(ty2);
printf("\n");
elem_print(e);
}
assert(_tysize[ty2] == REGSIZE);
/* Watch out for the case here where you are going to OP reg,EA */
/* and both the reg and EA use ES! Prevent this by forcing */
/* reg into the regular registers. */
if ((e2oper == OPind ||
(e2oper == OPvar && el_fl(e2) == FLfardata)) &&
!e2.Ecount)
{
retregs = ALLREGS;
}
codelem(cdb,e1,&retregs,test != 0);
reg = findreglsw(retregs); /* reg is the register with the offset*/
}
else
{
regm_t regm;
/* if (tyword + TYfptr) */
if (_tysize[ty1] == REGSIZE && _tysize[ty2] > REGSIZE)
{ retregs = ~*pretregs & ALLREGS;
/* if retregs doesn't have any regs in it that aren't reg vars */
if ((retregs & ~regcon.mvar) == 0)
retregs |= mAX;
}
else if (numwords == 2 && retregs & mES)
retregs = (retregs | mMSW) & ALLREGS;
// Determine if we should swap operands, because
// mov EAX,x
// add EAX,reg
// is faster than:
// mov EAX,reg
// add EAX,x
else if (e2oper == OPvar &&
e1.Eoper == OPvar &&
e.Eoper != OPmin &&
isregvar(e1,®m,null) &&
regm != retregs &&
_tysize[ty1] == _tysize[ty2])
{
elem *es = e1;
e1 = e2;
e2 = es;
}
codelem(cdb,e1,&retregs,test != 0); // eval left leaf
reg = findreg(retregs);
}
reg_t rreg;
int rval;
targ_size_t i;
switch (e2oper)
{
case OPind: /* if addressing mode */
if (!e2.Ecount) /* if not CSE */
goto L1; /* try OP reg,EA */
goto default;
default: /* operator node */
L2:
rretregs = ALLREGS & ~retregs;
/* Be careful not to do arithmetic on ES */
if (_tysize[ty1] == REGSIZE && _tysize[ty2] > REGSIZE && *pretregs != mPSW)
rretregs = *pretregs & (mES | ALLREGS | mBP) & ~retregs;
else if (isbyte)
rretregs &= BYTEREGS;
scodelem(cdb,e2,&rretregs,retregs,true); // get rvalue
rreg = (_tysize[ty2] > REGSIZE) ? findreglsw(rretregs) : findreg(rretregs);
if (!test)
getregs(cdb,retregs); // we will trash these regs
if (numwords == 1) /* ADD reg,rreg */
{
/* reverse operands to avoid moving around the segment value */
if (_tysize[ty2] > REGSIZE)
{
getregs(cdb,rretregs);
genregs(cdb,op1,rreg,reg);
retregs = rretregs; // reverse operands
}
else
{
genregs(cdb,op1,reg,rreg);
if (!I16 && *pretregs & mPSW)
cdb.last().Iflags |= word;
}
if (I64 && sz == 8)
code_orrex(cdb.last(), REX_W);
if (I64 && isbyte && (reg >= 4 || rreg >= 4))
code_orrex(cdb.last(), REX);
}
else /* numwords == 2 */ /* ADD lsreg,lsrreg */
{
reg = findreglsw(retregs);
rreg = findreglsw(rretregs);
genregs(cdb,op1,reg,rreg);
if (e.Eoper == OPadd || e.Eoper == OPmin)
code_orflag(cdb.last(),CFpsw);
reg = findregmsw(retregs);
rreg = findregmsw(rretregs);
if (!(e2oper == OPu16_32 && // if second operand is 0
(op2 == 0x0B || op2 == 0x33)) // and OR or XOR
)
genregs(cdb,op2,reg,rreg); // ADC msreg,msrreg
}
break;
case OPrelconst:
if (I64 && (config.flags3 & CFG3pic || config.exe == EX_WIN64))
goto default;
if (sz != REGSIZE)
goto L2;
if (segfl[el_fl(e2)] != 3) /* if not in data segment */
goto L2;
if (evalinregister(e2))
goto L2;
cs.IEV2.Voffset = e2.EV.Voffset;
cs.IEV2.Vsym = e2.EV.Vsym;
cs.Iflags |= CFoff;
i = 0; /* no INC or DEC opcode */
rval = 0;
goto L3;
case OPconst:
if (tyfv(ty2))
goto L2;
if (numwords == 1)
{
if (!el_signx32(e2))
goto L2;
i = e2.EV.Vpointer;
if (word)
{
if (!(*pretregs & mPSW) &&
config.flags4 & CFG4speed &&
(e.Eoper == OPor || e.Eoper == OPxor || test ||
(e1.Eoper != OPvar && e1.Eoper != OPind)))
{ word = 0;
i &= 0xFFFF;
}
}
rval = reghasvalue(isbyte ? BYTEREGS : ALLREGS,i,&rreg);
cs.IEV2.Vsize_t = i;
L3:
if (!test)
getregs(cdb,retregs); // we will trash these regs
op1 ^= isbyte;
cs.Iflags |= word;
if (rval)
{ cs.Iop = op1 ^ 2;
mode = rreg;
}
else
cs.Iop = 0x81;
cs.Irm = modregrm(3,mode&7,reg&7);
if (mode & 8)
cs.Irex |= REX_R;
if (reg & 8)
cs.Irex |= REX_B;
if (I64 && sz == 8)
cs.Irex |= REX_W;
if (I64 && isbyte && (reg >= 4 || (rval && rreg >= 4)))
cs.Irex |= REX;
cs.IFL2 = cast(ubyte)((e2.Eoper == OPconst) ? FLconst : el_fl(e2));
/* Modify instruction for special cases */
switch (e.Eoper)
{
case OPadd:
{
int iop;
if (i == 1)
iop = 0; /* INC reg */
else if (i == -1)
iop = 8; /* DEC reg */
else
break;
cs.Iop = (0x40 | iop | reg) ^ isbyte;
if ((isbyte && *pretregs & mPSW) || I64)
{
cs.Irm = cast(ubyte)(modregrm(3,0,reg & 7) | iop);
cs.Iop = 0xFF;
}
break;
}
case OPand:
if (test)
cs.Iop = rval ? op1 : 0xF7; // TEST
break;
default:
break;
}
if (*pretregs & mPSW)
cs.Iflags |= CFpsw;
cs.Iop ^= isbyte;
cdb.gen(&cs);
cs.Iflags &= ~CFpsw;
}
else if (numwords == 2)
{
getregs(cdb,retregs);
reg = findregmsw(retregs);
const lsreg = findreglsw(retregs);
cs.Iop = 0x81;
cs.Irm = modregrm(3,mode,lsreg);
cs.IFL2 = FLconst;
const msw = cast(targ_int)MSREG(e2.EV.Vllong);
cs.IEV2.Vint = e2.EV.Vlong;
switch (e.Eoper)
{
case OPadd:
case OPmin:
cs.Iflags |= CFpsw;
break;
default:
break;
}
cdb.gen(&cs);
cs.Iflags &= ~CFpsw;
cs.Irm = cast(ubyte)((cs.Irm & modregrm(3,7,0)) | reg);
cs.IEV2.Vint = msw;
if (e.Eoper == OPadd)
cs.Irm |= modregrm(0,2,0); /* ADC */
cdb.gen(&cs);
}
else
assert(0);
freenode(e2);
break;
case OPvar:
if (movOnly(e2))
goto L2;
L1:
if (tyfv(ty2))
goto L2;
if (!test)
getregs(cdb,retregs); // we will trash these regs
loadea(cdb,e2,&cs,op1,
((numwords == 2) ? findreglsw(retregs) : reg),
0,retregs,retregs);
if (!I16 && word)
{ if (*pretregs & mPSW)
code_orflag(cdb.last(),word);
else
cdb.last().Iflags &= ~cast(int)word;
}
else if (numwords == 2)
{
if (e.Eoper == OPadd || e.Eoper == OPmin)
code_orflag(cdb.last(),CFpsw);
reg = findregmsw(retregs);
if (!OTleaf(e2.Eoper))
{ getlvalue_msw(&cs);
cs.Iop = op2;
NEWREG(cs.Irm,reg);
cdb.gen(&cs); // ADC reg,data+2
}
else
loadea(cdb,e2,&cs,op2,reg,REGSIZE,retregs,0);
}
else if (I64 && sz == 8)
code_orrex(cdb.last(), REX_W);
freenode(e2);
break;
}
if (sz <= REGSIZE && *pretregs & mPSW)
{
/* If the expression is (_tls_array + ...), then the flags are not set
* since the linker may rewrite these instructions into something else.
*/
if (I64 && e.Eoper == OPadd && e1.Eoper == OPvar)
{
const s = e1.EV.Vsym;
if (s.Sident[0] == '_' && memcmp(s.Sident.ptr + 1,"tls_array".ptr,10) == 0)
{
goto L7; // don't assume flags are set
}
}
code_orflag(cdb.last(),CFpsw);
*pretregs &= ~mPSW; // flags already set
L7: { }
}
fixresult(cdb,e,retregs,pretregs);
}
/*****************************
* Handle multiply.
*/
void cdmul(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
//printf("cdmul()\n");
elem *e1 = e.EV.E1;
elem *e2 = e.EV.E2;
if (*pretregs == 0) // if don't want result
{
codelem(cdb,e1,pretregs,false); // eval left leaf
*pretregs = 0; // in case they got set
codelem(cdb,e2,pretregs,false);
return;
}
//printf("cdmul(e = %p, *pretregs = %s)\n", e, regm_str(*pretregs));
const tyml = tybasic(e1.Ety);
const ty = tybasic(e.Ety);
const oper = e.Eoper;
if (tyfloating(tyml))
{
if (tyvector(tyml) ||
config.fpxmmregs && oper != OPmod && tyxmmreg(tyml) &&
!(*pretregs & mST0) &&
!(ty == TYldouble || ty == TYildouble) && // watch out for shrinkLongDoubleConstantIfPossible()
!tycomplex(ty) && // SIMD code is not set up to deal with complex mul/div
!(ty == TYllong) // or passing to function through integer register
)
{
orthxmm(cdb,e,pretregs);
return;
}
static if (TARGET_LINUX || TARGET_OSX || TARGET_FREEBSD || TARGET_OPENBSD || TARGET_DRAGONFLYBSD || TARGET_SOLARIS)
orth87(cdb,e,pretregs);
else
opdouble(cdb,e,pretregs,(oper == OPmul) ? CLIB.dmul : CLIB.ddiv);
return;
}
if (tyxmmreg(tyml))
{
orthxmm(cdb,e,pretregs);
return;
}
const uns = tyuns(tyml) || tyuns(e2.Ety); // 1 if signed operation, 0 if unsigned
const isbyte = tybyte(e.Ety) != 0;
const sz = _tysize[tyml];
const ubyte rex = (I64 && sz == 8) ? REX_W : 0;
const uint grex = rex << 16;
const OPER opunslng = I16 ? OPu16_32 : OPu32_64;
code cs = void;
cs.Iflags = 0;
cs.Irex = 0;
switch (e2.Eoper)
{
case OPu16_32:
case OPs16_32:
case OPu32_64:
case OPs32_64:
{
if (sz != 2 * REGSIZE || e1.Eoper != e2.Eoper ||
e1.Ecount || e2.Ecount)
goto default;
const ubyte opx = (e2.Eoper == opunslng) ? 4 : 5;
regm_t retregsx = mAX;
codelem(cdb,e1.EV.E1,&retregsx,false); // eval left leaf
if (e2.EV.E1.Eoper == OPvar ||
(e2.EV.E1.Eoper == OPind && !e2.EV.E1.Ecount)
)
{
loadea(cdb,e2.EV.E1,&cs,0xF7,opx,0,mAX,mAX | mDX);
}
else
{
regm_t rretregsx = ALLREGS & ~mAX;
scodelem(cdb,e2.EV.E1,&rretregsx,retregsx,true); // get rvalue
getregs(cdb,mAX | mDX);
const rregx = findreg(rretregsx);
cdb.gen2(0xF7,grex | modregrmx(3,opx,rregx)); // OP AX,rregx
}
freenode(e.EV.E1);
freenode(e2);
fixresult(cdb,e,mAX | mDX,pretregs);
return;
}
case OPconst:
const e2factor = cast(targ_size_t)el_tolong(e2);
// Multiply by a constant
if (I32 && sz == REGSIZE * 2)
{