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iasmdmd.d
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iasmdmd.d
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/**
* Inline assembler implementation for DMD.
* https://dlang.org/spec/iasm.html
*
* Copyright: Copyright (c) 1992-1999 by Symantec
* Copyright (C) 1999-2020 by The D Language Foundation, All Rights Reserved
* Authors: Mike Cote, John Micco and $(LINK2 http://www.digitalmars.com, Walter Bright)
* License: $(LINK2 http://www.boost.org/LICENSE_1_0.txt, Boost License 1.0)
* Source: $(LINK2 https://github.com/dlang/dmd/blob/master/src/dmd/iasmdmd.d, _iasmdmd.d)
* Documentation: https://dlang.org/phobos/dmd_iasmdmd.html
* Coverage: https://codecov.io/gh/dlang/dmd/src/master/src/dmd/iasmdmd.d
*/
module dmd.iasmdmd;
import core.stdc.stdio;
import core.stdc.stdarg;
import core.stdc.stdlib;
import core.stdc.string;
import dmd.declaration;
import dmd.denum;
import dmd.dscope;
import dmd.dsymbol;
import dmd.errors;
import dmd.expression;
import dmd.expressionsem;
import dmd.globals;
import dmd.id;
import dmd.identifier;
import dmd.init;
import dmd.mtype;
import dmd.optimize;
import dmd.statement;
import dmd.target;
import dmd.tokens;
import dmd.root.ctfloat;
import dmd.root.rmem;
import dmd.root.rootobject;
import dmd.backend.cc;
import dmd.backend.cdef;
import dmd.backend.code;
import dmd.backend.code_x86;
import dmd.backend.codebuilder : CodeBuilder;
import dmd.backend.global;
import dmd.backend.iasm;
import dmd.backend.ptrntab : asm_opstr, asm_op_lookup, init_optab;
import dmd.backend.xmm;
//debug = EXTRA_DEBUG;
//debug = debuga;
/*******************************
* Clean up iasm things before exiting the compiler.
* Currently not called.
*/
version (none)
public void iasm_term()
{
if (asmstate.bInit)
{
asmstate.psDollar = null;
asmstate.psLocalsize = null;
asmstate.bInit = false;
}
}
/************************
* Perform semantic analysis on InlineAsmStatement.
* Params:
* s = inline asm statement
* sc = context
* Returns:
* `s` on success, ErrorStatement if errors happened
*/
public Statement inlineAsmSemantic(InlineAsmStatement s, Scope *sc)
{
//printf("InlineAsmStatement.semantic()\n");
OP *o;
OPND[4] opnds;
int nOps;
PTRNTAB ptb;
int usNumops;
asmstate.ucItype = 0;
asmstate.bReturnax = false;
asmstate.lbracketNestCount = 0;
asmstate.errors = false;
asmstate.statement = s;
asmstate.sc = sc;
version (none) // don't use bReturnax anymore, and will fail anyway if we use return type inference
{
// Scalar return values will always be in AX. So if it is a scalar
// then asm block sets return value if it modifies AX, if it is non-scalar
// then always assume that the ASM block sets up an appropriate return
// value.
asmstate.bReturnax = true;
if (sc.func.type.nextOf().isscalar())
asmstate.bReturnax = false;
}
if (!asmstate.bInit)
{
asmstate.bInit = true;
init_optab();
asmstate.psDollar = LabelDsymbol.create(Id._dollar);
asmstate.psLocalsize = Dsymbol.create(Id.__LOCAL_SIZE);
}
asmstate.loc = s.loc;
asmstate.tok = s.tokens;
asm_token_trans(asmstate.tok);
switch (asmstate.tokValue)
{
case cast(TOK)ASMTKnaked:
s.naked = true;
sc.func.naked = true;
asm_token();
break;
case cast(TOK)ASMTKeven:
asm_token();
s.asmalign = 2;
break;
case TOK.align_:
{
asm_token();
uint _align = asm_getnum();
if (ispow2(_align) == -1)
{
asmerr("`align %d` must be a power of 2", _align);
goto AFTER_EMIT;
}
else
s.asmalign = _align;
break;
}
// The following three convert the keywords 'int', 'in', 'out'
// to identifiers, since they are x86 instructions.
case TOK.int32:
o = asm_op_lookup(Id.__int.toChars());
goto Lopcode;
case TOK.in_:
o = asm_op_lookup(Id.___in.toChars());
goto Lopcode;
case TOK.out_:
o = asm_op_lookup(Id.___out.toChars());
goto Lopcode;
case TOK.identifier:
o = asm_op_lookup(asmstate.tok.ident.toChars());
if (!o)
goto OPCODE_EXPECTED;
Lopcode:
asmstate.ucItype = o.usNumops & ITMASK;
asm_token();
if (o.usNumops > 4)
{
switch (asmstate.ucItype)
{
case ITdata:
s.asmcode = asm_db_parse(o);
goto AFTER_EMIT;
case ITaddr:
s.asmcode = asm_da_parse(o);
goto AFTER_EMIT;
default:
break;
}
}
// get the first part of an expr
if (asmstate.tokValue != TOK.endOfFile)
{
foreach (i; 0 .. 4)
{
asm_cond_exp(opnds[i]);
if (asmstate.errors)
goto AFTER_EMIT;
nOps = i + 1;
if (asmstate.tokValue != TOK.comma)
break;
asm_token();
}
}
// match opcode and operands in ptrntab to verify legal inst and
// generate
ptb = asm_classify(o, opnds[0 .. nOps], usNumops);
if (asmstate.errors)
goto AFTER_EMIT;
assert(ptb.pptb0);
//
// The Multiply instruction takes 3 operands, but if only 2 are seen
// then the third should be the second and the second should
// be a duplicate of the first.
//
if (asmstate.ucItype == ITopt &&
nOps == 2 && usNumops == 2 &&
(ASM_GET_aopty(opnds[1].usFlags) == _imm) &&
((o.usNumops & ITSIZE) == 3))
{
nOps = 3;
opnds[2] = opnds[1];
opnds[1] = opnds[0];
// Re-classify the opcode because the first classification
// assumed 2 operands.
ptb = asm_classify(o, opnds[0 .. nOps], usNumops);
}
else
{
version (none)
{
if (asmstate.ucItype == ITshift && (ptb.pptb2.usOp2 == 0 ||
(ptb.pptb2.usOp2 & _cl)))
{
o2 = null;
usNumops = 1;
}
}
}
s.asmcode = asm_emit(s.loc, usNumops, ptb, o, opnds[0 .. nOps]);
break;
default:
OPCODE_EXPECTED:
asmerr("opcode expected, not `%s`", asmstate.tok.toChars());
break;
}
AFTER_EMIT:
if (asmstate.tokValue != TOK.endOfFile)
{
asmerr("end of instruction expected, not `%s`", asmstate.tok.toChars()); // end of line expected
}
return asmstate.errors ? new ErrorStatement() : s;
}
/**********************************
* Called from back end.
* Params: bp = asm block
* Returns: mask of registers used by block bp.
*/
extern (C++) public regm_t iasm_regs(block *bp)
{
debug (debuga)
printf("Block iasm regs = 0x%X\n", bp.usIasmregs);
refparam |= bp.bIasmrefparam;
return bp.usIasmregs;
}
private:
enum ADDFWAIT = false;
// Additional tokens for the inline assembler
alias ASMTK = int;
enum
{
ASMTKlocalsize = TOK.max_ + 1,
ASMTKdword,
ASMTKeven,
ASMTKfar,
ASMTKnaked,
ASMTKnear,
ASMTKptr,
ASMTKqword,
ASMTKseg,
ASMTKword,
ASMTKmax = ASMTKword-(TOK.max_+1)+1
}
immutable char*[ASMTKmax] apszAsmtk =
[
"__LOCAL_SIZE",
"dword",
"even",
"far",
"naked",
"near",
"ptr",
"qword",
"seg",
"word",
];
alias ucItype_t = ubyte;
enum
{
ITprefix = 0x10, /// special prefix
ITjump = 0x20, /// jump instructions CALL, Jxx and LOOPxx
ITimmed = 0x30, /// value of an immediate operand controls
/// code generation
ITopt = 0x40, /// not all operands are required
ITshift = 0x50, /// rotate and shift instructions
ITfloat = 0x60, /// floating point coprocessor instructions
ITdata = 0x70, /// DB, DW, DD, DQ, DT pseudo-ops
ITaddr = 0x80, /// DA (define addresss) pseudo-op
ITMASK = 0xF0,
ITSIZE = 0x0F, /// mask for size
}
struct ASM_STATE
{
ucItype_t ucItype; /// Instruction type
Loc loc;
bool bInit;
bool errors; /// true if semantic errors occurred
LabelDsymbol psDollar;
Dsymbol psLocalsize;
bool bReturnax;
InlineAsmStatement statement;
Scope* sc;
Token* tok;
TOK tokValue;
int lbracketNestCount;
}
__gshared ASM_STATE asmstate;
/**
* Describes a register
*
* This struct is only used for manifest constant
*/
struct REG
{
immutable:
string regstr;
ubyte val;
opflag_t ty;
bool isSIL_DIL_BPL_SPL() const
{
// Be careful as these have the same val's as AH CH DH BH
return ty == _r8 &&
((val == _SIL && regstr == "SIL") ||
(val == _DIL && regstr == "DIL") ||
(val == _BPL && regstr == "BPL") ||
(val == _SPL && regstr == "SPL"));
}
}
immutable REG regFp = { "ST", 0, _st };
immutable REG[8] aregFp =
[
{ "ST(0)", 0, _sti },
{ "ST(1)", 1, _sti },
{ "ST(2)", 2, _sti },
{ "ST(3)", 3, _sti },
{ "ST(4)", 4, _sti },
{ "ST(5)", 5, _sti },
{ "ST(6)", 6, _sti },
{ "ST(7)", 7, _sti }
];
enum // the x86 CPU numbers for these registers
{
_AL = 0,
_AH = 4,
_AX = 0,
_EAX = 0,
_BL = 3,
_BH = 7,
_BX = 3,
_EBX = 3,
_CL = 1,
_CH = 5,
_CX = 1,
_ECX = 1,
_DL = 2,
_DH = 6,
_DX = 2,
_EDX = 2,
_BP = 5,
_EBP = 5,
_SP = 4,
_ESP = 4,
_DI = 7,
_EDI = 7,
_SI = 6,
_ESI = 6,
_ES = 0,
_CS = 1,
_SS = 2,
_DS = 3,
_GS = 5,
_FS = 4,
}
immutable REG[71] regtab =
[
{"AL", _AL, _r8 | _al},
{"AH", _AH, _r8},
{"AX", _AX, _r16 | _ax},
{"EAX", _EAX, _r32 | _eax},
{"BL", _BL, _r8},
{"BH", _BH, _r8},
{"BX", _BX, _r16},
{"EBX", _EBX, _r32},
{"CL", _CL, _r8 | _cl},
{"CH", _CH, _r8},
{"CX", _CX, _r16},
{"ECX", _ECX, _r32},
{"DL", _DL, _r8},
{"DH", _DH, _r8},
{"DX", _DX, _r16 | _dx},
{"EDX", _EDX, _r32},
{"BP", _BP, _r16},
{"EBP", _EBP, _r32},
{"SP", _SP, _r16},
{"ESP", _ESP, _r32},
{"DI", _DI, _r16},
{"EDI", _EDI, _r32},
{"SI", _SI, _r16},
{"ESI", _ESI, _r32},
{"ES", _ES, _seg | _es},
{"CS", _CS, _seg | _cs},
{"SS", _SS, _seg | _ss },
{"DS", _DS, _seg | _ds},
{"GS", _GS, _seg | _gs},
{"FS", _FS, _seg | _fs},
{"CR0", 0, _special | _crn},
{"CR2", 2, _special | _crn},
{"CR3", 3, _special | _crn},
{"CR4", 4, _special | _crn},
{"DR0", 0, _special | _drn},
{"DR1", 1, _special | _drn},
{"DR2", 2, _special | _drn},
{"DR3", 3, _special | _drn},
{"DR4", 4, _special | _drn},
{"DR5", 5, _special | _drn},
{"DR6", 6, _special | _drn},
{"DR7", 7, _special | _drn},
{"TR3", 3, _special | _trn},
{"TR4", 4, _special | _trn},
{"TR5", 5, _special | _trn},
{"TR6", 6, _special | _trn},
{"TR7", 7, _special | _trn},
{"MM0", 0, _mm},
{"MM1", 1, _mm},
{"MM2", 2, _mm},
{"MM3", 3, _mm},
{"MM4", 4, _mm},
{"MM5", 5, _mm},
{"MM6", 6, _mm},
{"MM7", 7, _mm},
{"XMM0", 0, _xmm | _xmm0},
{"XMM1", 1, _xmm},
{"XMM2", 2, _xmm},
{"XMM3", 3, _xmm},
{"XMM4", 4, _xmm},
{"XMM5", 5, _xmm},
{"XMM6", 6, _xmm},
{"XMM7", 7, _xmm},
{"YMM0", 0, _ymm},
{"YMM1", 1, _ymm},
{"YMM2", 2, _ymm},
{"YMM3", 3, _ymm},
{"YMM4", 4, _ymm},
{"YMM5", 5, _ymm},
{"YMM6", 6, _ymm},
{"YMM7", 7, _ymm},
];
enum // 64 bit only registers
{
_RAX = 0,
_RBX = 3,
_RCX = 1,
_RDX = 2,
_RSI = 6,
_RDI = 7,
_RBP = 5,
_RSP = 4,
_R8 = 8,
_R9 = 9,
_R10 = 10,
_R11 = 11,
_R12 = 12,
_R13 = 13,
_R14 = 14,
_R15 = 15,
_R8D = 8,
_R9D = 9,
_R10D = 10,
_R11D = 11,
_R12D = 12,
_R13D = 13,
_R14D = 14,
_R15D = 15,
_R8W = 8,
_R9W = 9,
_R10W = 10,
_R11W = 11,
_R12W = 12,
_R13W = 13,
_R14W = 13,
_R15W = 15,
_SIL = 6,
_DIL = 7,
_BPL = 5,
_SPL = 4,
_R8B = 8,
_R9B = 9,
_R10B = 10,
_R11B = 11,
_R12B = 12,
_R13B = 13,
_R14B = 14,
_R15B = 15,
}
immutable REG[65] regtab64 =
[
{"RAX", _RAX, _r64 | _rax},
{"RBX", _RBX, _r64},
{"RCX", _RCX, _r64},
{"RDX", _RDX, _r64},
{"RSI", _RSI, _r64},
{"RDI", _RDI, _r64},
{"RBP", _RBP, _r64},
{"RSP", _RSP, _r64},
{"R8", _R8, _r64},
{"R9", _R9, _r64},
{"R10", _R10, _r64},
{"R11", _R11, _r64},
{"R12", _R12, _r64},
{"R13", _R13, _r64},
{"R14", _R14, _r64},
{"R15", _R15, _r64},
{"R8D", _R8D, _r32},
{"R9D", _R9D, _r32},
{"R10D", _R10D, _r32},
{"R11D", _R11D, _r32},
{"R12D", _R12D, _r32},
{"R13D", _R13D, _r32},
{"R14D", _R14D, _r32},
{"R15D", _R15D, _r32},
{"R8W", _R8W, _r16},
{"R9W", _R9W, _r16},
{"R10W", _R10W, _r16},
{"R11W", _R11W, _r16},
{"R12W", _R12W, _r16},
{"R13W", _R13W, _r16},
{"R14W", _R14W, _r16},
{"R15W", _R15W, _r16},
{"SIL", _SIL, _r8},
{"DIL", _DIL, _r8},
{"BPL", _BPL, _r8},
{"SPL", _SPL, _r8},
{"R8B", _R8B, _r8},
{"R9B", _R9B, _r8},
{"R10B", _R10B, _r8},
{"R11B", _R11B, _r8},
{"R12B", _R12B, _r8},
{"R13B", _R13B, _r8},
{"R14B", _R14B, _r8},
{"R15B", _R15B, _r8},
{"XMM8", 8, _xmm},
{"XMM9", 9, _xmm},
{"XMM10", 10, _xmm},
{"XMM11", 11, _xmm},
{"XMM12", 12, _xmm},
{"XMM13", 13, _xmm},
{"XMM14", 14, _xmm},
{"XMM15", 15, _xmm},
{"YMM8", 8, _ymm},
{"YMM9", 9, _ymm},
{"YMM10", 10, _ymm},
{"YMM11", 11, _ymm},
{"YMM12", 12, _ymm},
{"YMM13", 13, _ymm},
{"YMM14", 14, _ymm},
{"YMM15", 15, _ymm},
{"CR8", 8, _r64 | _special | _crn},
];
alias ASM_JUMPTYPE = int;
enum
{
ASM_JUMPTYPE_UNSPECIFIED,
ASM_JUMPTYPE_SHORT,
ASM_JUMPTYPE_NEAR,
ASM_JUMPTYPE_FAR
}
struct OPND
{
immutable(REG) *base; // if plain register
immutable(REG) *pregDisp1; // if [register1]
immutable(REG) *pregDisp2;
immutable(REG) *segreg; // if segment override
bool bOffset; // if 'offset' keyword
bool bSeg; // if 'segment' keyword
bool bPtr; // if 'ptr' keyword
uint uchMultiplier; // register multiplier; valid values are 0,1,2,4,8
opflag_t usFlags;
Dsymbol s;
targ_llong disp;
real_t vreal = 0.0;
Type ptype;
ASM_JUMPTYPE ajt;
}
/*******************************
*/
void asm_chktok(TOK toknum, const(char)* msg)
{
if (asmstate.tokValue != toknum)
{
/* When we run out of tokens, asmstate.tok is null.
* But when this happens when a ';' was hit.
*/
asmerr(msg, asmstate.tok ? asmstate.tok.toChars() : ";");
}
asm_token(); // keep consuming tokens
}
/*******************************
*/
PTRNTAB asm_classify(OP *pop, OPND[] opnds, out int outNumops)
{
opflag_t[4] opflags;
bool bInvalid64bit = false;
bool bRetry = false;
// How many arguments are there? the parser is strictly left to right
// so this should work.
foreach (i, ref opnd; opnds)
{
opnd.usFlags = opflags[i] = asm_determine_operand_flags(opnd);
}
const usNumops = cast(int)opnds.length;
// Now check to insure that the number of operands is correct
auto usActual = (pop.usNumops & ITSIZE);
void paramError()
{
asmerr("%u operands found for `%s` instead of the expected %d", usNumops, asm_opstr(pop), usActual);
}
if (usActual != usNumops && asmstate.ucItype != ITopt &&
asmstate.ucItype != ITfloat)
{
paramError();
}
if (usActual < usNumops)
outNumops = usActual;
else
outNumops = usNumops;
void TYPE_SIZE_ERROR()
{
foreach (i, ref opnd; opnds)
{
if (ASM_GET_aopty(opnd.usFlags) == _reg)
continue;
opflags[i] = opnd.usFlags = (opnd.usFlags & ~0x1F) | OpndSize._anysize;
if(asmstate.ucItype != ITjump)
continue;
if (i == 0 && bRetry && opnd.s && !opnd.s.isLabel())
{
asmerr("label expected", opnd.s.toChars());
return;
}
opnd.usFlags |= CONSTRUCT_FLAGS(0, 0, 0, _fanysize);
}
if (bRetry)
{
if(bInvalid64bit)
asmerr("operand for `%s` invalid in 64bit mode", asm_opstr(pop));
else
asmerr("bad type/size of operands `%s`", asm_opstr(pop));
return;
}
bRetry = true;
}
PTRNTAB returnIt(PTRNTAB ret)
{
if (bRetry)
{
asmerr("bad type/size of operands `%s`", asm_opstr(pop));
}
return ret;
}
void printMismatches(int usActual)
{
printOperands(pop, opnds);
printf("OPCODE mismatch = ");
foreach (i; 0 .. usActual)
{
if (i < opnds.length)
asm_output_flags(opnds[i].usFlags);
else
printf("NONE");
}
printf("\n");
}
//
// The number of arguments matches, now check to find the opcode
// in the associated opcode table
//
RETRY:
//printf("usActual = %d\n", usActual);
switch (usActual)
{
case 0:
if (global.params.is64bit && (pop.ptb.pptb0.usFlags & _i64_bit))
{
asmerr("opcode `%s` is unavailable in 64bit mode", asm_opstr(pop)); // illegal opcode in 64bit mode
break;
}
if ((asmstate.ucItype == ITopt ||
asmstate.ucItype == ITfloat) &&
usNumops != 0)
{
paramError();
break;
}
return returnIt(pop.ptb);
case 1:
{
enum log = false;
if (log) { printf("`%s`\n", asm_opstr(pop)); }
if (log) { printf("opflags1 = "); asm_output_flags(opflags[0]); printf("\n"); }
if (pop.ptb.pptb1.opcode == 0xE8 &&
opnds[0].s == asmstate.psDollar &&
(opnds[0].disp >= byte.min && opnds[0].disp <= byte.max)
)
// Rewrite CALL $+disp from rel8 to rel32
opflags[0] = CONSTRUCT_FLAGS(OpndSize._32, _rel, _flbl, 0);
PTRNTAB1 *table1;
for (table1 = pop.ptb.pptb1; table1.opcode != ASM_END;
table1++)
{
if (log) { printf("table = "); asm_output_flags(table1.usOp1); printf("\n"); }
const bMatch1 = asm_match_flags(opflags[0], table1.usOp1);
if (log) { printf("bMatch1 = x%x\n", bMatch1); }
if (bMatch1)
{
if (table1.opcode == 0x68 &&
table1.usOp1 == _imm16
)
// Don't match PUSH imm16 in 32 bit code
continue;
// Check if match is invalid in 64bit mode
if (global.params.is64bit && (table1.usFlags & _i64_bit))
{
bInvalid64bit = true;
continue;
}
// Check for ambiguous size
if (getOpndSize(opflags[0]) == OpndSize._anysize &&
!opnds[0].bPtr &&
(table1 + 1).opcode != ASM_END &&
getOpndSize(table1.usOp1) == OpndSize._8)
{
asmerr("operand size for opcode `%s` is ambiguous, add `ptr byte/short/int/long` prefix", asm_opstr(pop));
break RETRY;
}
break;
}
if ((asmstate.ucItype == ITimmed) &&
asm_match_flags(opflags[0],
CONSTRUCT_FLAGS(OpndSize._32_16_8, _imm, _normal,
0)) &&
opnds[0].disp == table1.usFlags)
break;
if (asmstate.ucItype == ITopt ||
asmstate.ucItype == ITfloat)
{
switch (usNumops)
{
case 0:
if (!table1.usOp1)
goto Lfound1;
break;
case 1:
break;
default:
paramError();
break RETRY;
}
}
}
Lfound1:
if (table1.opcode != ASM_END)
{
PTRNTAB ret = { pptb1 : table1 };
return returnIt(ret);
}
debug (debuga) printMismatches(usActual);
TYPE_SIZE_ERROR();
if (asmstate.errors)
break;
goto RETRY;
}
case 2:
{
enum log = false;
if (log) { printf("`%s`\n", asm_opstr(pop)); }
if (log) { printf("`%s`\n", asm_opstr(pop)); }
if (log) { printf("opflags1 = "); asm_output_flags(opflags[0]); printf("\n"); }
if (log) { printf("opflags2 = "); asm_output_flags(opflags[1]); printf("\n"); }
PTRNTAB2 *table2;
for (table2 = pop.ptb.pptb2;
table2.opcode != ASM_END;
table2++)
{
if (log) { printf("table1 = "); asm_output_flags(table2.usOp1); printf("\n"); }
if (log) { printf("table2 = "); asm_output_flags(table2.usOp2); printf("\n"); }
if (global.params.is64bit && (table2.usFlags & _i64_bit))
asmerr("opcode `%s` is unavailable in 64bit mode", asm_opstr(pop));
const bMatch1 = asm_match_flags(opflags[0], table2.usOp1);
const bMatch2 = asm_match_flags(opflags[1], table2.usOp2);
if (log) printf("match1 = %d, match2 = %d\n",bMatch1,bMatch2);
if (bMatch1 && bMatch2)
{
if (log) printf("match\n");
/* Don't match if implicit sign-extension will
* change the value of the immediate operand
*/
if (!bRetry && ASM_GET_aopty(table2.usOp2) == _imm)
{
OpndSize op1size = getOpndSize(table2.usOp1);
if (!op1size) // implicit register operand
{
switch (ASM_GET_uRegmask(table2.usOp1))
{
case ASM_GET_uRegmask(_al):
case ASM_GET_uRegmask(_cl): op1size = OpndSize._8; break;
case ASM_GET_uRegmask(_ax):
case ASM_GET_uRegmask(_dx): op1size = OpndSize._16; break;
case ASM_GET_uRegmask(_eax): op1size = OpndSize._32; break;
case ASM_GET_uRegmask(_rax): op1size = OpndSize._64; break;
default:
assert(0);
}
}
if (op1size > getOpndSize(table2.usOp2))
{
switch(getOpndSize(table2.usOp2))
{
case OpndSize._8:
if (opnds[1].disp > byte.max)
continue;
break;
case OpndSize._16:
if (opnds[1].disp > short.max)
continue;
break;
case OpndSize._32:
if (opnds[1].disp > int.max)
continue;
break;
default:
assert(0);
}
}
}
// Check for ambiguous size
if (asmstate.ucItype == ITopt &&
getOpndSize(opflags[0]) == OpndSize._anysize &&
!opnds[0].bPtr &&
opflags[1] == 0 &&
table2.usOp2 == 0 &&
(table2 + 1).opcode != ASM_END &&
getOpndSize(table2.usOp1) == OpndSize._8)
{
asmerr("operand size for opcode `%s` is ambiguous, add `ptr byte/short/int/long` prefix", asm_opstr(pop));
break RETRY;
}
break;
}
if (asmstate.ucItype == ITopt ||
asmstate.ucItype == ITfloat)
{
switch (usNumops)
{
case 0:
if (!table2.usOp1)
goto Lfound2;
break;
case 1:
if (bMatch1 && !table2.usOp2)
goto Lfound2;
break;
case 2:
break;
default:
paramError();
break RETRY;
}
}
version (none)
{
if (asmstate.ucItype == ITshift &&
!table2.usOp2 &&
bMatch1 && opnds[1].disp == 1 &&
asm_match_flags(opflags2,
CONSTRUCT_FLAGS(OpndSize._32_16_8, _imm,_normal,0))
)
break;
}
}
Lfound2:
if (table2.opcode != ASM_END)
{
PTRNTAB ret = { pptb2 : table2 };
return returnIt(ret);
}
debug (debuga) printMismatches(usActual);
TYPE_SIZE_ERROR();
if (asmstate.errors)
break;
goto RETRY;
}
case 3:
{
enum log = false;
if (log) { printf("`%s`\n", asm_opstr(pop)); }
if (log) { printf("opflags1 = "); asm_output_flags(opflags[0]); printf("\n"); }
if (log) { printf("opflags2 = "); asm_output_flags(opflags[1]); printf("\n"); }
if (log) { printf("opflags3 = "); asm_output_flags(opflags[2]); printf("\n"); }
PTRNTAB3 *table3;
for (table3 = pop.ptb.pptb3;
table3.opcode != ASM_END;
table3++)
{
if (log) { printf("table1 = "); asm_output_flags(table3.usOp1); printf("\n"); }
if (log) { printf("table2 = "); asm_output_flags(table3.usOp2); printf("\n"); }
if (log) { printf("table3 = "); asm_output_flags(table3.usOp3); printf("\n"); }
const bMatch1 = asm_match_flags(opflags[0], table3.usOp1);
const bMatch2 = asm_match_flags(opflags[1], table3.usOp2);
const bMatch3 = asm_match_flags(opflags[2], table3.usOp3);
if (bMatch1 && bMatch2 && bMatch3)