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cod1.c
4422 lines (4114 loc) · 147 KB
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cod1.c
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// Copyright (C) 1984-1998 by Symantec
// Copyright (C) 2000-2012 by Digital Mars
// All Rights Reserved
// http://www.digitalmars.com
// Written by Walter Bright
/*
* This source file is made available for personal use
* only. The license is in backendlicense.txt
* For any other uses, please contact Digital Mars.
*/
#if !SPP
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#if __sun || _MSC_VER
#include <alloca.h>
#endif
#include "cc.h"
#include "el.h"
#include "oper.h"
#include "code.h"
#include "global.h"
#include "type.h"
#include "xmm.h"
static char __file__[] = __FILE__; /* for tassert.h */
#include "tassert.h"
/* Generate the appropriate ESC instruction */
#define ESC(MF,b) (0xD8 + ((MF) << 1) + (b))
enum MF
{ // Values for MF
MFfloat = 0,
MFlong = 1,
MFdouble = 2,
MFword = 3
};
code * genf2(code *c,unsigned op,unsigned rm);
targ_size_t paramsize(elem *e,unsigned stackalign);
STATIC code * funccall (elem *,unsigned,unsigned,regm_t *,regm_t);
/* array to convert from index register to r/m field */
/* AX CX DX BX SP BP SI DI */
static const signed char regtorm32[8] = { 0, 1, 2, 3,-1, 5, 6, 7 };
signed char regtorm [8] = { -1,-1,-1, 7,-1, 6, 4, 5 };
/**************************
* Determine if e is a 32 bit scaled index addressing mode.
* Returns:
* 0 not a scaled index addressing mode
* !=0 the value for ss in the SIB byte
*/
int isscaledindex(elem *e)
{ targ_uns ss;
assert(!I16);
while (e->Eoper == OPcomma)
e = e->E2;
if (!(e->Eoper == OPshl && !e->Ecount &&
e->E2->Eoper == OPconst &&
(ss = e->E2->EV.Vuns) <= 3
)
)
ss = 0;
return ss;
}
/*********************************************
* Generate code for which isscaledindex(e) returned a non-zero result.
*/
code *cdisscaledindex(elem *e,regm_t *pidxregs,regm_t keepmsk)
{ code *c;
regm_t r;
// Load index register with result of e->E1
c = NULL;
while (e->Eoper == OPcomma)
{
r = 0;
c = cat(c,scodelem(e->E1,&r,keepmsk,TRUE));
freenode(e);
e = e->E2;
}
assert(e->Eoper == OPshl);
c = cat(c,scodelem(e->E1,pidxregs,keepmsk,TRUE));
freenode(e->E2);
freenode(e);
return c;
}
/***********************************
* Determine index if we can do two LEA instructions as a multiply.
* Returns:
* 0 can't do it
*/
static struct Ssindex
{
targ_uns product;
char ss1;
char ss2;
char ssflags;
#define SSFLnobp 1 // can't have EBP in relconst
#define SSFLnobase1 2 // no base register for first LEA
#define SSFLnobase 4 // no base register
#define SSFLlea 8 // can do it in one LEA
} ssindex_array[] =
{ {0, 0,0}, // [0] is a place holder
{3, 1,0,SSFLnobp | SSFLlea},
{5, 2,0,SSFLnobp | SSFLlea},
{9, 3,0,SSFLnobp | SSFLlea},
{6, 1,1,SSFLnobase},
{12,1,2,SSFLnobase},
{24,1,3,SSFLnobase},
{10,2,1,SSFLnobase},
{20,2,2,SSFLnobase},
{40,2,3,SSFLnobase},
{18,3,1,SSFLnobase},
{36,3,2,SSFLnobase},
{72,3,3,SSFLnobase},
{15,2,1,SSFLnobp},
{25,2,2,SSFLnobp},
{27,3,1,SSFLnobp},
{45,3,2,SSFLnobp},
{81,3,3,SSFLnobp},
{16,3,1,SSFLnobase1 | SSFLnobase},
{32,3,2,SSFLnobase1 | SSFLnobase},
{64,3,3,SSFLnobase1 | SSFLnobase},
};
int ssindex(int op,targ_uns product)
{ int i;
if (op == OPshl)
product = 1 << product;
for (i = 1; i < arraysize(ssindex_array); i++)
{
if (ssindex_array[i].product == product)
return i;
}
return 0;
}
/***************************************
* Build an EA of the form disp[base][index*scale].
* Input:
* c struct to fill in
* base base register (-1 if none)
* index index register (-1 if none)
* scale scale factor - 1,2,4,8
* disp displacement
*/
void buildEA(code *c,int base,int index,int scale,targ_size_t disp)
{ unsigned char rm;
unsigned char sib;
unsigned char rex = 0;
sib = 0;
if (!I16)
{ unsigned ss;
assert(index != SP);
switch (scale)
{ case 1: ss = 0; break;
case 2: ss = 1; break;
case 4: ss = 2; break;
case 8: ss = 3; break;
default: assert(0);
}
if (base == -1)
{
if (index == -1)
rm = modregrm(0,0,5);
else
{
rm = modregrm(0,0,4);
sib = modregrm(ss,index & 7,5);
if (index & 8)
rex |= REX_X;
}
}
else if (index == -1)
{
if (base == SP)
{
rm = modregrm(2,0,4);
sib = modregrm(0,4,SP);
}
else
{ rm = modregrm(2,0,base & 7);
if (base & 8)
{ rex |= REX_B;
if (base == R12)
{
rm = modregrm(2,0,4);
sib = modregrm(0,4,4);
}
}
}
}
else
{
rm = modregrm(2,0,4);
sib = modregrm(ss,index & 7,base & 7);
if (index & 8)
rex |= REX_X;
if (base & 8)
rex |= REX_B;
}
}
else
{
// -1 AX CX DX BX SP BP SI DI
static unsigned char EA16rm[9][9] =
{
{ 0x06,0x09,0x09,0x09,0x87,0x09,0x86,0x84,0x85, }, // -1
{ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, }, // AX
{ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, }, // CX
{ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, }, // DX
{ 0x87,0x09,0x09,0x09,0x09,0x09,0x09,0x80,0x81, }, // BX
{ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, }, // SP
{ 0x86,0x09,0x09,0x09,0x09,0x09,0x09,0x82,0x83, }, // BP
{ 0x84,0x09,0x09,0x09,0x80,0x09,0x82,0x09,0x09, }, // SI
{ 0x85,0x09,0x09,0x09,0x81,0x09,0x83,0x09,0x09, } // DI
};
assert(scale == 1);
rm = EA16rm[base + 1][index + 1];
assert(rm != 9);
}
c->Irm = rm;
c->Isib = sib;
c->Irex = rex;
c->IFL1 = FLconst;
c->IEV1.Vuns = disp;
}
/*********************************************
* Build REX, modregrm and sib bytes
*/
unsigned buildModregrm(int mod, int reg, int rm)
{ unsigned m;
if (I16)
m = modregrm(mod, reg, rm);
else
{
if ((rm & 7) == SP && mod != 3)
m = (modregrm(0,4,SP) << 8) | modregrm(mod,reg & 7,4);
else
m = modregrm(mod,reg & 7,rm & 7);
if (reg & 8)
m |= REX_R << 16;
if (rm & 8)
m |= REX_B << 16;
}
return m;
}
/****************************************
* Generate code for eecontext
*/
void genEEcode()
{ regm_t retregs;
code *c;
eecontext.EEin++;
regcon.immed.mval = 0;
retregs = 0; //regmask(eecontext.EEelem->Ety);
assert(EEStack.offset >= REGSIZE);
c = cod3_stackadj(NULL, EEStack.offset - REGSIZE);
gen1(c,0x50 + SI); // PUSH ESI
genadjesp(c,EEStack.offset);
c = gencodelem(c,eecontext.EEelem,&retregs, FALSE);
assignaddrc(c);
pinholeopt(c,NULL);
jmpaddr(c);
eecontext.EEcode = gen1(c,0xCC); // INT 3
eecontext.EEin--;
}
/********************************************
* Gen a save/restore sequence for mask of registers.
* Returns:
* amount of stack consumed
*/
unsigned gensaverestore2(regm_t regm,code **csave,code **crestore)
{
code *cs1 = *csave;
code *cs2 = *crestore;
unsigned stackused = 0;
//printf("gensaverestore2(%s)\n", regm_str(regm));
regm &= mBP | mES | ALLREGS | XMMREGS | mST0 | mST01;
for (int i = 0; regm; i++)
{
if (regm & 1)
{
if (i == ES)
{
stackused += REGSIZE;
cs1 = gen1(cs1, 0x06); // PUSH ES
cs2 = cat(gen1(CNIL, 0x07),cs2); // POP ES
}
else if (i == ST0 || i == ST01)
{
gensaverestore87(1 << i, &cs1, &cs2);
}
else if (i >= XMM0 || I64)
{ unsigned idx;
cs1 = regsave.save(cs1, i, &idx);
cs2 = regsave.restore(cs2, i, idx);
}
else
{
stackused += REGSIZE;
cs1 = gen1(cs1,0x50 + (i & 7)); // PUSH i
code *c = gen1(NULL, 0x58 + (i & 7)); // POP i
if (i & 8)
{ code_orrex(cs1, REX_B);
code_orrex(c, REX_B);
}
cs2 = cat(c,cs2);
}
}
regm >>= 1;
}
*csave = cs1;
*crestore = cs2;
return stackused;
}
unsigned gensaverestore(regm_t regm,code **csave,code **crestore)
{
*csave = NULL;
*crestore = NULL;
return gensaverestore2(regm, csave, crestore);
}
/****************************************
* Clean parameters off stack.
* Input:
* numpara amount to adjust stack pointer
* keepmsk mask of registers to not destroy
*/
code *genstackclean(code *c,unsigned numpara,regm_t keepmsk)
{
//dbg_printf("genstackclean(numpara = %d, stackclean = %d)\n",numpara,cgstate.stackclean);
if (numpara && (cgstate.stackclean || STACKALIGN == 16))
{
#if 0 // won't work if operand of scodelem
if (numpara == stackpush && // if this is all those pushed
needframe && // and there will be a BP
!config.windows &&
!(regcon.mvar & fregsaved) // and no registers will be pushed
)
c = genregs(c,0x89,BP,SP); // MOV SP,BP
else
#endif
{ regm_t scratchm = 0;
if (numpara == REGSIZE && config.flags4 & CFG4space)
{
scratchm = ALLREGS & ~keepmsk & regcon.used & ~regcon.mvar;
}
if (scratchm)
{ unsigned r;
c = cat(c,allocreg(&scratchm,&r,TYint));
c = gen1(c,0x58 + r); // POP r
}
else
c = cod3_stackadj(c, -numpara);
}
stackpush -= numpara;
c = genadjesp(c,-numpara);
}
return c;
}
/*********************************
* Generate code for a logical expression.
* Input:
* e elem
* jcond
* bit 1 if TRUE then goto jump address if e
* if FALSE then goto jump address if !e
* 2 don't call save87()
* fltarg FLcode or FLblock, flavor of target if e evaluates to jcond
* targ either code or block pointer to destination
*/
code *logexp(elem *e,int jcond,unsigned fltarg,code *targ)
{ code *c,*ce,*cnop;
regm_t retregs;
unsigned op;
//printf("logexp(e = %p, jcond = %d)\n", e, jcond);
int no87 = (jcond & 2) == 0;
_chkstack();
code *cc = docommas(&e); // scan down commas
cgstate.stackclean++;
if (EOP(e) && !e->Ecount) /* if operator and not common sub */
{ con_t regconsave;
switch (e->Eoper)
{ case OPoror:
if (jcond & 1)
{ c = logexp(e->E1,jcond,fltarg,targ);
regconsave = regcon;
ce = logexp(e->E2,jcond,fltarg,targ);
}
else
{ cnop = gennop(CNIL);
c = logexp(e->E1,jcond | 1,FLcode,cnop);
regconsave = regcon;
ce = logexp(e->E2,jcond,fltarg,targ);
ce = cat(ce,cnop);
}
cnop = CNIL;
goto L1;
case OPandand:
if (jcond & 1)
{ cnop = gennop(CNIL); /* a dummy target address */
c = logexp(e->E1,jcond & ~1,FLcode,cnop);
regconsave = regcon;
ce = logexp(e->E2,jcond,fltarg,targ);
}
else
{ c = logexp(e->E1,jcond,fltarg,targ);
regconsave = regcon;
ce = logexp(e->E2,jcond,fltarg,targ);
cnop = CNIL;
}
L1: andregcon(®consave);
freenode(e);
c = cat4(cc,c,ce,cnop);
goto Lret;
case OPnot:
jcond ^= 1;
case OPbool:
case OPs8_16:
case OPu8_16:
case OPs16_32:
case OPu16_32:
case OPs32_64:
case OPu32_64:
case OPu32_d:
case OPd_ld:
c = logexp(e->E1,jcond,fltarg,targ);
freenode(e);
goto Lretc;
case OPcond:
{
code *cnop2 = gennop(CNIL); // addresses of start of leaves
cnop = gennop(CNIL);
c = logexp(e->E1,FALSE,FLcode,cnop2); /* eval condition */
con_t regconold = regcon;
ce = logexp(e->E2->E1,jcond,fltarg,targ);
ce = genjmp(ce,JMP,FLcode,(block *) cnop); /* skip second leaf */
regconsave = regcon;
regcon = regconold;
code_next(cnop2) = logexp(e->E2->E2,jcond,fltarg,targ);
andregcon(®conold);
andregcon(®consave);
freenode(e->E2);
freenode(e);
c = cat6(cc,c,NULL,ce,cnop2,cnop);
goto Lret;
}
}
}
/* Special code for signed long compare.
* Not necessary for I64 until we do cents.
*/
if (OTrel2(e->Eoper) && /* if < <= >= > */
!e->Ecount &&
( (I16 && tybasic(e->E1->Ety) == TYlong && tybasic(e->E2->Ety) == TYlong) ||
(I32 && tybasic(e->E1->Ety) == TYllong && tybasic(e->E2->Ety) == TYllong))
)
{
c = longcmp(e,jcond,fltarg,targ);
goto Lretc;
}
retregs = mPSW; /* return result in flags */
op = jmpopcode(e); /* get jump opcode */
if (!(jcond & 1))
op ^= 0x101; // toggle jump condition(s)
c = codelem(e,&retregs,TRUE); /* evaluate elem */
if (no87)
c = cat(c,cse_flush(no87)); // flush CSE's to memory
genjmp(c,op,fltarg,(block *) targ); /* generate jmp instruction */
Lretc:
c = cat(cc,c);
Lret:
cgstate.stackclean--;
return c;
}
/******************************
* Routine to aid in setting things up for gen().
* Look for common subexpression.
* Can handle indirection operators, but not if they're common subs.
* Input:
* e -> elem where we get some of the data from
* cs -> partially filled code to add
* op = opcode
* reg = reg field of (mod reg r/m)
* offset = data to be added to Voffset field
* keepmsk = mask of registers we must not destroy
* desmsk = mask of registers destroyed by executing the instruction
* Returns:
* pointer to code generated
*/
code *loadea(elem *e,code *cs,unsigned op,unsigned reg,targ_size_t offset,
regm_t keepmsk,regm_t desmsk)
{
code *c,*cg,*cd;
#ifdef DEBUG
if (debugw)
printf("loadea: e=%p cs=%p op=x%x reg=%d offset=%lld keepmsk=%s desmsk=%s\n",
e,cs,op,reg,(unsigned long long)offset,regm_str(keepmsk),regm_str(desmsk));
#endif
assert(e);
cs->Iflags = 0;
cs->Irex = 0;
cs->Iop = op;
tym_t tym = e->Ety;
int sz = tysize(tym);
/* Determine if location we want to get is in a register. If so, */
/* substitute the register for the EA. */
/* Note that operators don't go through this. CSE'd operators are */
/* picked up by comsub(). */
if (e->Ecount && /* if cse */
e->Ecount != e->Ecomsub && /* and cse was generated */
op != 0x8D && op != 0xC4 && /* and not an LEA or LES */
(op != 0xFF || reg != 3) && /* and not CALLF MEM16 */
(op & 0xFFF8) != 0xD8) // and not 8087 opcode
{
assert(!EOP(e)); /* can't handle this */
regm_t rm = regcon.cse.mval & ~regcon.cse.mops & ~regcon.mvar; // possible regs
if (sz > REGSIZE) // value is in 2 or 4 registers
{
if (I16 && sz == 8) // value is in 4 registers
{ static regm_t rmask[4] = { mDX,mCX,mBX,mAX };
rm &= rmask[offset >> 1];
}
else if (offset)
rm &= mMSW; /* only high words */
else
rm &= mLSW; /* only low words */
}
for (unsigned i = 0; rm; i++)
{ if (mask[i] & rm)
{ if (regcon.cse.value[i] == e && // if register has elem
/* watch out for a CWD destroying DX */
!(i == DX && op == 0xF7 && desmsk & mDX))
{
/* if ES, then it can only be a load */
if (i == ES)
{ if (op != 0x8B)
goto L1; /* not a load */
cs->Iop = 0x8C; /* MOV reg,ES */
cs->Irm = modregrm(3,0,reg & 7);
if (reg & 8)
code_orrex(cs, REX_B);
}
else // XXX reg,i
{
cs->Irm = modregrm(3,reg & 7,i & 7);
if (reg & 8)
cs->Irex |= REX_R;
if (i & 8)
cs->Irex |= REX_B;
if (sz == 1 && I64 && (i >= 4 || reg >= 4))
cs->Irex |= REX;
if (I64 && (sz == 8 || sz == 16))
cs->Irex |= REX_W;
}
c = CNIL;
goto L2;
}
rm &= ~mask[i];
}
}
}
L1:
c = getlvalue(cs,e,keepmsk);
if (offset == REGSIZE)
getlvalue_msw(cs);
else
cs->IEVoffset1 += offset;
if (I64)
{ if (reg >= 4 && sz == 1) // if byte register
// Can only address those 8 bit registers if a REX byte is present
cs->Irex |= REX;
if ((op & 0xFFFFFFF8) == 0xD8)
cs->Irex &= ~REX_W; // not needed for x87 ops
}
code_newreg(cs, reg); // OR in reg field
if (!I16)
{
if (reg == 6 && op == 0xFF || /* don't PUSH a word */
op == 0x0FB7 || op == 0x0FBF || /* MOVZX/MOVSX */
(op & 0xFFF8) == 0xD8 || /* 8087 instructions */
op == 0x8D) /* LEA */
{
cs->Iflags &= ~CFopsize;
if (reg == 6 && op == 0xFF) // if PUSH
cs->Irex &= ~REX_W; // REX is ignored for PUSH anyway
}
}
else if ((op & 0xFFF8) == 0xD8 && ADDFWAIT())
cs->Iflags |= CFwait;
L2:
cg = getregs(desmsk); /* save any regs we destroy */
/* KLUDGE! fix up DX for divide instructions */
cd = CNIL;
if (op == 0xF7 && desmsk == (mAX|mDX)) /* if we need to fix DX */
{ if (reg == 7) /* if IDIV */
{ cd = gen1(cd,0x99); // CWD
if (I64 && sz == 8)
code_orrex(cd, REX_W);
}
else if (reg == 6) // if DIV
{ cd = genregs(cd,0x33,DX,DX); // XOR DX,DX
}
}
// Eliminate MOV reg,reg
if ((cs->Iop & ~3) == 0x88 &&
(cs->Irm & 0xC7) == modregrm(3,0,reg & 7))
{
unsigned r = cs->Irm & 7;
if (cs->Irex & REX_B)
r |= 8;
if (r == reg)
cs->Iop = NOP;
}
return cat4(c,cg,cd,gen(NULL,cs));
}
/**************************
* Get addressing mode.
*/
unsigned getaddrmode(regm_t idxregs)
{
unsigned mode;
if (I16)
{
mode = (idxregs & mBX) ? modregrm(2,0,7) : /* [BX] */
(idxregs & mDI) ? modregrm(2,0,5): /* [DI] */
(idxregs & mSI) ? modregrm(2,0,4): /* [SI] */
(assert(0),1);
}
else
{ unsigned reg = findreg(idxregs & (ALLREGS | mBP));
if (reg == R12)
mode = (REX_B << 16) | (modregrm(0,4,4) << 8) | modregrm(2,0,4);
else
mode = modregrmx(2,0,reg);
}
return mode;
}
void setaddrmode(code *c, regm_t idxregs)
{
unsigned mode = getaddrmode(idxregs);
c->Irm = mode & 0xFF;
c->Isib = mode >> 8;
c->Irex &= ~REX_B;
c->Irex |= mode >> 16;
}
/**********************************************
*/
void getlvalue_msw(code *c)
{
if (c->IFL1 == FLreg)
{
unsigned regmsw = c->IEVsym1->Sregmsw;
c->Irm = (c->Irm & ~7) | (regmsw & 7);
if (regmsw & 8)
c->Irex |= REX_B;
else
c->Irex &= ~REX_B;
}
else
c->IEVoffset1 += REGSIZE;
}
/**********************************************
*/
void getlvalue_lsw(code *c)
{
if (c->IFL1 == FLreg)
{
unsigned reglsw = c->IEVsym1->Sreglsw;
c->Irm = (c->Irm & ~7) | (reglsw & 7);
if (reglsw & 8)
c->Irex |= REX_B;
else
c->Irex &= ~REX_B;
}
else
c->IEVoffset1 -= REGSIZE;
}
/******************
* Compute addressing mode.
* Generate & return sequence of code (if any).
* Return in cs the info on it.
* Input:
* pcs -> where to store data about addressing mode
* e -> the lvalue elem
* keepmsk mask of registers we must not destroy or use
* if (keepmsk & RMstore), this will be only a store operation
* into the lvalue
* if (keepmsk & RMload), this will be a read operation only
*/
code *getlvalue(code *pcs,elem *e,regm_t keepmsk)
{ regm_t idxregs;
unsigned fl,f,opsave;
code *c;
elem *e1;
elem *e11;
elem *e12;
bool e1isadd,e1free;
unsigned reg;
tym_t e1ty;
symbol *s;
//printf("getlvalue(e = %p, keepmsk = %s)\n",e,regm_str(keepmsk));
//elem_print(e);
assert(e);
elem_debug(e);
if (e->Eoper == OPvar || e->Eoper == OPrelconst)
{ s = e->EV.sp.Vsym;
fl = s->Sfl;
if (tyfloating(s->ty()))
objmod->fltused();
}
else
fl = FLoper;
pcs->IFL1 = fl;
pcs->Iflags = CFoff; /* only want offsets */
pcs->Irex = 0;
pcs->IEVoffset1 = 0;
tym_t ty = e->Ety;
unsigned sz = tysize(ty);
if (tyfloating(ty))
objmod->fltused();
if (I64 && (sz == 8 || sz == 16) && !tyvector(ty))
pcs->Irex |= REX_W;
if (!I16 && sz == SHORTSIZE)
pcs->Iflags |= CFopsize;
if (ty & mTYvolatile)
pcs->Iflags |= CFvolatile;
c = CNIL;
switch (fl)
{
#if 0 && TARGET_LINUX
case FLgot:
case FLgotoff:
gotref = 1;
pcs->IEVsym1 = s;
pcs->IEVoffset1 = e->EV.sp.Voffset;
if (e->Eoper == OPvar && fl == FLgot)
{
code *c1;
unsigned saveop = pcs->Iop;
idxregs = allregs & ~keepmsk; // get a scratch register
c = allocreg(&idxregs,®,TYptr);
pcs->Irm = modregrm(2,reg,BX); // BX has GOT
pcs->Isib = 0;
//pcs->Iflags |= CFvolatile;
pcs->Iop = 0x8B;
c = gen(c,pcs); // MOV reg,disp[EBX]
pcs->Irm = modregrm(0,0,reg);
pcs->IEVoffset1 = 0;
pcs->Iop = saveop;
}
else
{
pcs->Irm = modregrm(2,0,BX); // disp[EBX] is addr
pcs->Isib = 0;
}
break;
#endif
case FLoper:
#ifdef DEBUG
if (debugw) printf("getlvalue(e = %p, keepmsk = %s)\n", e, regm_str(keepmsk));
#endif
switch (e->Eoper)
{
case OPadd: // this way when we want to do LEA
e1 = e;
e1free = FALSE;
e1isadd = TRUE;
break;
case OPind:
case OPpostinc: // when doing (*p++ = ...)
case OPpostdec: // when doing (*p-- = ...)
case OPbt:
case OPbtc:
case OPbtr:
case OPbts:
e1 = e->E1;
e1free = TRUE;
e1isadd = e1->Eoper == OPadd;
break;
default:
#ifdef DEBUG
elem_print(e);
#endif
assert(0);
}
e1ty = tybasic(e1->Ety);
if (e1isadd)
{ e12 = e1->E2;
e11 = e1->E1;
}
/* First see if we can replace *(e+&v) with
* MOV idxreg,e
* EA = [ES:] &v+idxreg
*/
f = FLconst;
if (e1isadd &&
((e12->Eoper == OPrelconst
#if TARGET_SEGMENTED
&& (f = el_fl(e12)) != FLfardata
#endif
) ||
(e12->Eoper == OPconst && !I16 && !e1->Ecount && (!I64 || el_signx32(e12)))) &&
!(I64 && (config.flags3 & CFG3pic || config.exe == EX_WIN64)) &&
e1->Ecount == e1->Ecomsub &&
#if TARGET_SEGMENTED
(!e1->Ecount || (~keepmsk & ALLREGS & mMSW) || (e1ty != TYfptr && e1ty != TYhptr)) &&
#endif
tysize(e11->Ety) == REGSIZE
)
{ unsigned char t; /* component of r/m field */
int ss;
int ssi;
#if !TARGET_SEGMENTED
if (e12->Eoper == OPrelconst)
f = el_fl(e12);
#endif
/*assert(datafl[f]);*/ /* what if addr of func? */
if (!I16)
{ /* Any register can be an index register */
regm_t idxregs = allregs & ~keepmsk;
assert(idxregs);
/* See if e1->E1 can be a scaled index */
ss = isscaledindex(e11);
if (ss)
{
/* Load index register with result of e11->E1 */
c = cdisscaledindex(e11,&idxregs,keepmsk);
reg = findreg(idxregs);
{
t = stackfl[f] ? 2 : 0;
pcs->Irm = modregrm(t,0,4);
pcs->Isib = modregrm(ss,reg & 7,5);
if (reg & 8)
pcs->Irex |= REX_X;
}
}
else if ((e11->Eoper == OPmul || e11->Eoper == OPshl) &&
!e11->Ecount &&
e11->E2->Eoper == OPconst &&
(ssi = ssindex(e11->Eoper,e11->E2->EV.Vuns)) != 0
)
{
regm_t scratchm;
#if 0 && TARGET_LINUX
assert(f != FLgot && f != FLgotoff);
#endif
char ssflags = ssindex_array[ssi].ssflags;
if (ssflags & SSFLnobp && stackfl[f])
goto L6;
// Load index register with result of e11->E1
c = scodelem(e11->E1,&idxregs,keepmsk,TRUE);
reg = findreg(idxregs);
int ss1 = ssindex_array[ssi].ss1;
if (ssflags & SSFLlea)
{
assert(!stackfl[f]);
pcs->Irm = modregrm(2,0,4);
pcs->Isib = modregrm(ss1,reg & 7,reg & 7);
if (reg & 8)
pcs->Irex |= REX_X | REX_B;
}
else
{ int rbase;
unsigned r;
scratchm = ALLREGS & ~keepmsk;
c = cat(c,allocreg(&scratchm,&r,TYint));
if (ssflags & SSFLnobase1)
{ t = 0;
rbase = 5;
}
else
{ t = 0;
rbase = reg;
if (rbase == BP || rbase == R13)
{ static unsigned imm32[4] = {1+1,2+1,4+1,8+1};
// IMUL r,BP,imm32
c = genc2(c,0x69,modregxrmx(3,r,rbase),imm32[ss1]);
goto L7;
}
}
c = gen2sib(c,0x8D,modregxrm(t,r,4),modregrm(ss1,reg & 7,rbase & 7));
if (reg & 8)
code_orrex(c, REX_X);
if (rbase & 8)
code_orrex(c, REX_B);
if (I64)
code_orrex(c, REX_W);
if (ssflags & SSFLnobase1)
{ code_last(c)->IFL1 = FLconst;
code_last(c)->IEV1.Vuns = 0;
}
L7:
if (ssflags & SSFLnobase)
{ t = stackfl[f] ? 2 : 0;
rbase = 5;
}
else
{ t = 2;
rbase = r;
assert(rbase != BP);
}
pcs->Irm = modregrm(t,0,4);
pcs->Isib = modregrm(ssindex_array[ssi].ss2,r & 7,rbase & 7);
if (r & 8)
pcs->Irex |= REX_X;
if (rbase & 8)
pcs->Irex |= REX_B;
}
freenode(e11->E2);
freenode(e11);
}
else
{
L6:
/* Load index register with result of e11 */