/
cod4.c
3367 lines (3118 loc) · 111 KB
/
cod4.c
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// Copyright (C) 1985-1998 by Symantec
// Copyright (C) 2000-2011 by Digital Mars
// All Rights Reserved
// http://www.digitalmars.com
// Written by Walter Bright
/*
* This source file is made available for personal use
* only. The license is in /dmd/src/dmd/backendlicense.txt
* or /dm/src/dmd/backendlicense.txt
* For any other uses, please contact Digital Mars.
*/
#if !SPP
#include <stdio.h>
#include <time.h>
#include "cc.h"
#include "el.h"
#include "oper.h"
#include "code.h"
#include "type.h"
#include "global.h"
static char __file__[] = __FILE__; /* for tassert.h */
#include "tassert.h"
/* AX,CX,DX,BX */
const unsigned dblreg[4] = { BX,DX,(unsigned)-1,CX };
/*******************************
* Return number of times symbol s appears in tree e.
*/
STATIC int intree(symbol *s,elem *e)
{
if (EOP(e))
return intree(s,e->E1) + (EBIN(e) ? intree(s,e->E2) : 0);
return e->Eoper == OPvar && e->EV.sp.Vsym == s;
}
/***********************************
* Determine if expression e can be evaluated directly into register
* variable s.
* Have to be careful about things like x=x+x+x, and x=a+x.
* Returns:
* !=0 can
* 0 can't
*/
STATIC int doinreg(symbol *s, elem *e)
{ int in = 0;
int op;
L1:
op = e->Eoper;
if (op == OPind ||
OTcall(op) ||
OTleaf(op) ||
(in = intree(s,e)) == 0 ||
(OTunary(op) && !EOP(e->E1))
)
return 1;
if (in == 1)
{
switch (op)
{
case OPadd:
case OPmin:
case OPand:
case OPor:
case OPxor:
case OPshl:
case OPmul:
if (!intree(s,e->E2))
{
e = e->E1;
goto L1;
}
}
}
return 0;
}
/****************************
* Return code for saving common subexpressions if EA
* turns out to be a register.
* This is called just before modifying an EA.
*/
code *modEA(code *c)
{
if ((c->Irm & 0xC0) == 0xC0) // addressing mode refers to a register
{
unsigned reg = c->Irm & 7;
if (c->Irex & REX_B)
{ reg |= 8;
assert(I64);
}
return getregs(mask[reg]);
}
return CNIL;
}
#if TARGET_WINDOS
// This code is for CPUs that do not support the 8087
/****************************
* Gen code for op= for doubles.
*/
STATIC code * opassdbl(elem *e,regm_t *pretregs,unsigned op)
{ code *c1,*c2,*c3,*c4,*c5,*c6,cs;
unsigned clib;
regm_t retregs2,retregs,idxregs;
tym_t tym;
elem *e1;
static unsigned clibtab[OPdivass - OPpostinc + 1] =
/* OPpostinc,OPpostdec,OPeq,OPaddass,OPminass,OPmulass,OPdivass */
{ CLIBdadd, CLIBdsub, (unsigned)-1, CLIBdadd,CLIBdsub,CLIBdmul,CLIBddiv };
if (config.inline8087)
return opass87(e,pretregs);
clib = clibtab[op - OPpostinc];
e1 = e->E1;
tym = tybasic(e1->Ety);
c1 = getlvalue(&cs,e1,DOUBLEREGS | mBX | mCX);
if (tym == TYfloat)
{
clib += CLIBfadd - CLIBdadd; /* convert to float operation */
/* Load EA into FLOATREGS */
c1 = cat(c1,getregs(FLOATREGS));
cs.Iop = 0x8B;
cs.Irm |= modregrm(0,AX,0);
c1 = gen(c1,&cs);
if (!I32)
{
cs.Irm |= modregrm(0,DX,0);
getlvalue_msw(&cs);
c1 = gen(c1,&cs);
getlvalue_lsw(&cs);
}
retregs2 = FLOATREGS2;
idxregs = FLOATREGS | idxregm(&cs);
retregs = FLOATREGS;
}
else
{
if (I32)
{
/* Load EA into DOUBLEREGS */
c1 = cat(c1,getregs(DOUBLEREGS_32));
cs.Iop = 0x8B;
cs.Irm |= modregrm(0,AX,0);
c1 = gen(c1,&cs);
cs.Irm |= modregrm(0,DX,0);
getlvalue_msw(&cs);
c1 = gen(c1,&cs);
getlvalue_lsw(&cs);
retregs2 = DOUBLEREGS2_32;
idxregs = DOUBLEREGS_32 | idxregm(&cs);
}
else
{
/* Push EA onto stack */
cs.Iop = 0xFF;
cs.Irm |= modregrm(0,6,0);
cs.IEVoffset1 += DOUBLESIZE - REGSIZE;
c1 = gen(c1,&cs);
getlvalue_lsw(&cs);
gen(c1,&cs);
getlvalue_lsw(&cs);
gen(c1,&cs);
getlvalue_lsw(&cs);
gen(c1,&cs);
stackpush += DOUBLESIZE;
retregs2 = DOUBLEREGS_16;
idxregs = idxregm(&cs);
}
retregs = DOUBLEREGS;
}
if ((cs.Iflags & CFSEG) == CFes)
idxregs |= mES;
cgstate.stackclean++;
c3 = scodelem(e->E2,&retregs2,idxregs,FALSE);
cgstate.stackclean--;
c4 = callclib(e,clib,&retregs,0);
if (e1->Ecount)
cssave(e1,retregs,EOP(e1)); /* if lvalue is a CSE */
freenode(e1);
cs.Iop = 0x89; /* MOV EA,DOUBLEREGS */
c5 = fltregs(&cs,tym);
c6 = fixresult(e,retregs,pretregs);
return cat6(c1,CNIL,c3,c4,c5,c6);
}
/****************************
* Gen code for OPnegass for doubles.
*/
STATIC code * opnegassdbl(elem *e,regm_t *pretregs)
{ code *c1,*c2,*c3,*c,*cl,*cr,cs;
unsigned clib;
regm_t retregs2,retregs,idxregs;
tym_t tym;
elem *e1;
int sz;
if (config.inline8087)
return cdnegass87(e,pretregs);
e1 = e->E1;
tym = tybasic(e1->Ety);
sz = tysize[tym];
cl = getlvalue(&cs,e1,*pretregs ? DOUBLEREGS | mBX | mCX : 0);
cr = modEA(&cs);
cs.Irm |= modregrm(0,6,0);
cs.Iop = 0x80;
cs.IEVoffset1 += sz - 1;
cs.IFL2 = FLconst;
cs.IEV2.Vuns = 0x80;
c = gen(NULL,&cs); // XOR 7[EA],0x80
if (tycomplex(tym))
{
cs.IEVoffset1 -= sz / 2;
gen(c,&cs); // XOR 7[EA],0x80
}
c = cat3(cl,cr,c);
if (*pretregs || e1->Ecount)
{
cs.IEVoffset1 -= sz - 1;
if (tym == TYfloat)
{
// Load EA into FLOATREGS
c1 = getregs(FLOATREGS);
cs.Iop = 0x8B;
NEWREG(cs.Irm, AX);
c1 = gen(c1,&cs);
if (!I32)
{
NEWREG(cs.Irm, DX);
getlvalue_msw(&cs);
c1 = gen(c1,&cs);
getlvalue_lsw(&cs);
}
retregs = FLOATREGS;
}
else
{
if (I32)
{
// Load EA into DOUBLEREGS
c1 = getregs(DOUBLEREGS_32);
cs.Iop = 0x8B;
cs.Irm &= ~modregrm(0,7,0);
cs.Irm |= modregrm(0,AX,0);
c1 = gen(c1,&cs);
cs.Irm |= modregrm(0,DX,0);
getlvalue_msw(&cs);
c1 = gen(c1,&cs);
getlvalue_lsw(&cs);
}
else
{
#if 1
cs.Iop = 0x8B;
c1 = fltregs(&cs,TYdouble); // MOV DOUBLEREGS, EA
#else
// Push EA onto stack
cs.Iop = 0xFF;
cs.Irm |= modregrm(0,6,0);
cs.IEVoffset1 += DOUBLESIZE - REGSIZE;
c1 = gen(NULL,&cs);
cs.IEVoffset1 -= REGSIZE;
gen(c1,&cs);
cs.IEVoffset1 -= REGSIZE;
gen(c1,&cs);
cs.IEVoffset1 -= REGSIZE;
gen(c1,&cs);
stackpush += DOUBLESIZE;
#endif
}
retregs = DOUBLEREGS;
}
if (e1->Ecount)
cssave(e1,retregs,EOP(e1)); /* if lvalue is a CSE */
}
else
{ retregs = 0;
assert(e1->Ecount == 0);
c1 = NULL;
}
freenode(e1);
c3 = fixresult(e,retregs,pretregs);
return cat3(c,c1,c3);
}
#endif
/************************
* Generate code for an assignment.
*/
code *cdeq(elem *e,regm_t *pretregs)
{
tym_t tymll;
unsigned reg;
int i;
code *cl,*cr,*c,cs;
elem *e11;
bool regvar; /* TRUE means evaluate into register variable */
regm_t varregm;
unsigned varreg;
targ_int postinc;
//printf("cdeq(e = %p, *pretregs = %s)\n", e, regm_str(*pretregs));
elem *e1 = e->E1;
elem *e2 = e->E2;
int e2oper = e2->Eoper;
tym_t tyml = tybasic(e1->Ety); /* type of lvalue */
regm_t retregs = *pretregs;
if (tyfloating(tyml) && config.inline8087)
{
if (tycomplex(tyml))
return complex_eq87(e, pretregs);
if (!(retregs == 0 &&
(e2oper == OPconst || e2oper == OPvar || e2oper == OPind))
)
return eq87(e,pretregs);
if (config.target_cpu >= TARGET_PentiumPro &&
(e2oper == OPvar || e2oper == OPind)
)
return eq87(e,pretregs);
if (tyml == TYldouble || tyml == TYildouble)
return eq87(e,pretregs);
}
unsigned sz = tysize[tyml]; // # of bytes to transfer
assert((int)sz > 0);
if (retregs == 0) /* if no return value */
{ int fl;
if ((e2oper == OPconst || /* if rvalue is a constant */
e2oper == OPrelconst &&
!(I64 && config.flags3 & CFG3pic) &&
((fl = el_fl(e2)) == FLdata ||
fl==FLudata || fl == FLextern) &&
!(e2->EV.sp.Vsym->ty() & mTYcs)
) &&
!evalinregister(e2) &&
!e1->Ecount) /* and no CSE headaches */
{
// Look for special case of (*p++ = ...), where p is a register variable
if (e1->Eoper == OPind &&
((e11 = e1->E1)->Eoper == OPpostinc || e11->Eoper == OPpostdec) &&
e11->E1->Eoper == OPvar &&
e11->E1->EV.sp.Vsym->Sfl == FLreg &&
(!I16 || e11->E1->EV.sp.Vsym->Sregm & IDXREGS)
)
{
postinc = e11->E2->EV.Vint;
if (e11->Eoper == OPpostdec)
postinc = -postinc;
cl = getlvalue(&cs,e11,RMstore);
freenode(e11->E2);
}
else
{ postinc = 0;
cl = getlvalue(&cs,e1,RMstore);
if (e2oper == OPconst &&
config.flags4 & CFG4speed &&
(config.target_cpu == TARGET_Pentium ||
config.target_cpu == TARGET_PentiumMMX) &&
(cs.Irm & 0xC0) == 0x80
)
{
if (I64 && sz == 8 && e2->EV.Vpointer)
{
// MOV reg,imm64
// MOV EA,reg
regm_t rregm = allregs & ~idxregm(&cs);
unsigned reg;
cl = regwithvalue(cl,rregm,e2->EV.Vpointer,®,64);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,reg & 7,0);
if (reg & 8)
cs.Irex |= REX_R;
c = gen(cl,&cs);
freenode(e2);
goto Lp;
}
if ((sz == REGSIZE || (I64 && sz == 4)) && e2->EV.Vint)
{
// MOV reg,imm
// MOV EA,reg
regm_t rregm = allregs & ~idxregm(&cs);
unsigned reg;
cl = regwithvalue(cl,rregm,e2->EV.Vint,®,0);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,reg & 7,0);
if (reg & 8)
cs.Irex |= REX_R;
c = gen(cl,&cs);
freenode(e2);
goto Lp;
}
if (sz == 2 * REGSIZE && e2->EV.Vllong == 0)
{ regm_t rregm;
unsigned reg;
// MOV reg,imm
// MOV EA,reg
// MOV EA+2,reg
rregm = getscratch() & ~idxregm(&cs);
if (rregm)
{ cl = regwithvalue(cl,rregm,e2->EV.Vint,®,0);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,reg,0);
c = gen(cl,&cs);
getlvalue_msw(&cs);
c = gen(c,&cs);
freenode(e2);
goto Lp;
}
}
}
}
/* If loading result into a register */
if ((cs.Irm & 0xC0) == 0xC0)
{ cl = cat(cl,modEA(&cs));
if (sz == 2 * REGSIZE && cs.IFL1 == FLreg)
cl = cat(cl,getregs(cs.IEVsym1->Sregm));
}
cs.Iop = (sz == 1) ? 0xC6 : 0xC7;
if (e2oper == OPrelconst)
{
cs.IEVoffset2 = e2->EV.sp.Voffset;
cs.IFL2 = fl;
cs.IEVsym2 = e2->EV.sp.Vsym;
cs.Iflags |= CFoff;
cl = gen(cl,&cs); /* MOV EA,&variable */
if (I64 && sz == 8)
code_orrex(cl, REX_W);
if (sz > REGSIZE)
{
cs.Iop = 0x8C;
getlvalue_msw(&cs);
cs.Irm |= modregrm(0,3,0);
cl = gen(cl,&cs); /* MOV EA+2,DS */
}
}
else
{
assert(e2oper == OPconst);
cs.IFL2 = FLconst;
targ_size_t *p = (targ_size_t *) &(e2->EV);
cs.IEV2.Vsize_t = *p;
// Look for loading a register variable
if ((cs.Irm & 0xC0) == 0xC0)
{ unsigned reg = cs.Irm & 7;
if (cs.Irex & REX_B)
reg |= 8;
if (I64 && sz == 8)
cl = movregconst(cl,reg,*p,64);
else
cl = movregconst(cl,reg,*p,1 ^ (cs.Iop & 1));
if (sz == 2 * REGSIZE)
{ getlvalue_msw(&cs);
cl = movregconst(cl,cs.Irm & 7,p[1],0);
}
}
else if (I64 && sz == 8 && *p >= 0x80000000)
{ // Use 64 bit MOV, as the 32 bit one gets sign extended
// MOV reg,imm64
// MOV EA,reg
regm_t rregm = allregs & ~idxregm(&cs);
unsigned reg;
cl = regwithvalue(cl,rregm,e2->EV.Vpointer,®,64);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,reg & 7,0);
if (reg & 8)
cs.Irex |= REX_R;
c = gen(cl,&cs);
freenode(e2);
goto Lp;
}
else
{ int regsize;
i = sz;
do
{ regsize = REGSIZE;
retregs = (sz == 1) ? BYTEREGS : allregs;
if (i >= 4 && I16 && I386)
{
regsize = 4;
cs.Iflags |= CFopsize; // use opsize to do 32 bit operation
}
else
{
if (reghasvalue(retregs,*p,®))
{
cs.Iop = (cs.Iop & 1) | 0x88;
cs.Irm |= modregrm(0,reg & 7,0); // MOV EA,reg
if (reg & 8)
cs.Irex |= REX_R;
if (I64 && sz == 1 && reg >= 4)
cs.Irex |= REX;
}
if (!I16 && i == 2) // if 16 bit operand
cs.Iflags |= CFopsize;
if (I64 && sz == 8)
cs.Irex |= REX_W;
}
cl = gen(cl,&cs); /* MOV EA,const */
p = (targ_size_t *)((char *) p + regsize);
cs.Iop = (cs.Iop & 1) | 0xC6;
cs.Irm &= ~modregrm(0,7,0);
cs.Irex &= ~REX_R;
cs.IEVoffset1 += regsize;
cs.IEV2.Vint = *p;
i -= regsize;
} while (i > 0);
}
}
freenode(e2);
c = cl;
goto Lp;
}
retregs = allregs; /* pick a reg, any reg */
if (sz == 2 * REGSIZE)
retregs &= ~mBP; // BP cannot be used for register pair
}
if (retregs == mPSW)
{ retregs = allregs;
if (sz == 2 * REGSIZE)
retregs &= ~mBP; // BP cannot be used for register pair
}
cs.Iop = 0x89;
if (sz == 1) // must have byte regs
{ cs.Iop = 0x88;
retregs &= BYTEREGS;
if (!retregs)
retregs = BYTEREGS;
}
else if (retregs & mES &&
((e1->Eoper == OPind &&
((tymll = tybasic(e1->E1->Ety)) == TYfptr || tymll == TYhptr))
||
(e1->Eoper == OPvar && e1->EV.sp.Vsym->Sfl == FLfardata)
)
)
// getlvalue() needs ES, so we can't return it
retregs = allregs; /* no conflicts with ES */
else if (tyml == TYdouble || tyml == TYdouble_alias || retregs & mST0)
retregs = DOUBLEREGS;
regvar = FALSE;
varregm = 0;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1->EV.sp.Vsym,e2) && // and we can compute directly into it
!(sz == 1 && e1->EV.sp.Voffset == 1)
)
{ regvar = TRUE;
retregs = varregm;
reg = varreg; /* evaluate directly in target register */
if (tysize(e1->Ety) == REGSIZE &&
tysize(e1->EV.sp.Vsym->Stype->Tty) == 2 * REGSIZE)
{
if (e1->EV.sp.Voffset)
retregs &= mMSW;
else
retregs &= mLSW;
reg = findreg(retregs);
}
}
}
if (*pretregs & mPSW && !EOP(e1)) /* if evaluating e1 couldn't change flags */
{ /* Be careful that this lines up with jmpopcode() */
retregs |= mPSW;
*pretregs &= ~mPSW;
}
cr = scodelem(e2,&retregs,0,TRUE); /* get rvalue */
// Look for special case of (*p++ = ...), where p is a register variable
if (e1->Eoper == OPind &&
((e11 = e1->E1)->Eoper == OPpostinc || e11->Eoper == OPpostdec) &&
e11->E1->Eoper == OPvar &&
e11->E1->EV.sp.Vsym->Sfl == FLreg &&
(!I16 || e11->E1->EV.sp.Vsym->Sregm & IDXREGS)
)
{
postinc = e11->E2->EV.Vint;
if (e11->Eoper == OPpostdec)
postinc = -postinc;
cl = getlvalue(&cs,e11,RMstore | retregs);
freenode(e11->E2);
if (I64 && sz < 8)
cs.Irex &= ~REX_W; // incorrectly set by getlvalue()
}
else
{ postinc = 0;
cl = getlvalue(&cs,e1,RMstore | retregs); // get lvalue (cl == CNIL if regvar)
}
c = getregs_imm(varregm);
assert(!(retregs & mES && (cs.Iflags & CFSEG) == CFes));
if ((tyml == TYfptr || tyml == TYhptr) && retregs & mES)
{
reg = findreglsw(retregs);
cs.Irm |= modregrm(0,reg,0);
c = gen(c,&cs); /* MOV EA,reg */
getlvalue_msw(&cs); // point to where segment goes
cs.Iop = 0x8C;
NEWREG(cs.Irm,0);
gen(c,&cs); /* MOV EA+2,ES */
}
else
{
if (!I16)
{
reg = findreg(retregs &
((sz > REGSIZE) ? mBP | mLSW : mBP | ALLREGS));
cs.Irm |= modregrm(0,reg & 7,0);
if (reg & 8)
cs.Irex |= REX_R;
for (; TRUE; sz -= REGSIZE)
{
// Do not generate mov from register onto itself
if (regvar && reg == ((cs.Irm & 7) | (cs.Irex & REX_B ? 8 : 0)))
break;
if (sz == 2) // if 16 bit operand
cs.Iflags |= CFopsize;
else if (sz == 1 && reg >= 4)
cs.Irex |= REX;
c = gen(c,&cs); // MOV EA+offset,reg
if (sz <= REGSIZE)
break;
getlvalue_msw(&cs);
reg = findregmsw(retregs);
code_newreg(&cs, reg);
}
}
else
{
if (sz > REGSIZE)
cs.IEVoffset1 += sz - REGSIZE; /* 0,2,6 */
reg = findreg(retregs &
(sz > REGSIZE ? mMSW : ALLREGS));
if (tyml == TYdouble || tyml == TYdouble_alias)
reg = AX;
cs.Irm |= modregrm(0,reg,0);
/* Do not generate mov from register onto itself */
if (!regvar || reg != (cs.Irm & 7))
for (; TRUE; sz -= REGSIZE) /* 1,2,4 */
{
c = gen(c,&cs); /* MOV EA+offset,reg */
if (sz <= REGSIZE)
break;
cs.IEVoffset1 -= REGSIZE;
if (tyml == TYdouble || tyml == TYdouble_alias)
reg = dblreg[reg];
else
reg = findreglsw(retregs);
NEWREG(cs.Irm,reg);
}
}
}
if (e1->Ecount || /* if lvalue is a CSE or */
regvar) /* rvalue can't be a CSE */
{
c = cat(c,getregs_imm(retregs)); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,EOP(e1)); /* if lvalue is a CSE */
}
c = cat4(cr,cl,c,fixresult(e,retregs,pretregs));
Lp:
if (postinc)
{
int reg = findreg(idxregm(&cs));
if (*pretregs & mPSW)
{ // Use LEA to avoid touching the flags
unsigned rm = cs.Irm & 7;
if (cs.Irex & REX_B)
rm |= 8;
c = genc1(c,0x8D,buildModregrm(2,reg,rm),FLconst,postinc);
if (sz == 8)
code_orrex(c, REX_W);
}
else if (I64)
{
c = genc2(c,0x81,modregrmx(3,0,reg),postinc);
if (tysize(e11->E1->Ety) == 8)
code_orrex(c, REX_W);
}
else
{
if (postinc == 1)
c = gen1(c,0x40 + reg); // INC reg
else if (postinc == -(targ_int)1)
c = gen1(c,0x48 + reg); // DEC reg
else
{
c = genc2(c,0x81,modregrm(3,0,reg),postinc);
}
}
}
freenode(e1);
return c;
}
/************************
* Generate code for += -= &= |= ^= negass
*/
code *cdaddass(elem *e,regm_t *pretregs)
{ regm_t retregs,forccs,forregs;
tym_t tyml;
unsigned reg,op,op1,op2,mode,wantres;
int byte;
code *cl,*cr,*c,*ce,cs;
elem *e1;
elem *e2;
unsigned opsize;
unsigned reverse;
int sz;
regm_t varregm;
unsigned varreg;
unsigned cflags;
//printf("cdaddass(e=%p, *pretregs = x%x)\n",e,*pretregs);
op = e->Eoper;
retregs = 0;
reverse = 0;
e1 = e->E1;
tyml = tybasic(e1->Ety); // type of lvalue
sz = tysize[tyml];
byte = (sz == 1); // 1 for byte operation, else 0
if (tyfloating(tyml))
{
#if TARGET_LINUX || TARGET_OSX || TARGET_FREEBSD || TARGET_OPENBSD || TARGET_SOLARIS
if (op == OPnegass)
c = cdnegass87(e,pretregs);
else
c = opass87(e,pretregs);
#else
if (op == OPnegass)
c = opnegassdbl(e,pretregs);
else
c = opassdbl(e,pretregs,op);
#endif
return c;
}
opsize = (I16 && tylong(tyml) && config.target_cpu >= TARGET_80386)
? CFopsize : 0;
cflags = 0;
forccs = *pretregs & mPSW; // return result in flags
forregs = *pretregs & ~mPSW; // return result in regs
/* TRUE if we want the result in a register */
wantres = forregs || (e1->Ecount && EOP(e1));
switch (op) /* select instruction opcodes */
{ case OPpostinc: op = OPaddass; /* i++ => += */
case OPaddass: op1 = 0x01; op2 = 0x11;
cflags = CFpsw;
mode = 0; break; /* ADD, ADC */
case OPpostdec: op = OPminass; /* i-- => -= */
case OPminass: op1 = 0x29; op2 = 0x19;
cflags = CFpsw;
mode = 5; break; /* SUB, SBC */
case OPandass: op1 = op2 = 0x21;
mode = 4; break; /* AND, AND */
case OPorass: op1 = op2 = 0x09;
mode = 1; break; /* OR , OR */
case OPxorass: op1 = op2 = 0x31;
mode = 6; break; /* XOR, XOR */
case OPnegass: op1 = 0xF7; // NEG
break;
default:
assert(0);
}
op1 ^= byte; /* bit 0 is 0 for byte operation */
if (op == OPnegass)
{
cl = getlvalue(&cs,e1,0);
cr = modEA(&cs);
cs.Irm |= modregrm(0,3,0);
cs.Iop = op1;
switch (tysize[tyml])
{ case CHARSIZE:
c = gen(CNIL,&cs);
break;
case SHORTSIZE:
c = gen(CNIL,&cs);
if (!I16 && *pretregs & mPSW)
c->Iflags |= CFopsize | CFpsw;
break;
case LONGSIZE:
if (!I16 || opsize)
{ c = gen(CNIL,&cs);
c->Iflags |= opsize;
break;
}
neg_2reg:
getlvalue_msw(&cs);
c = gen(CNIL,&cs); // NEG EA+2
getlvalue_lsw(&cs);
gen(c,&cs); // NEG EA
code_orflag(c,CFpsw);
cs.Iop = 0x81;
getlvalue_msw(&cs);
cs.IFL2 = FLconst;
cs.IEV2.Vuns = 0;
gen(c,&cs); // SBB EA+2,0
break;
case LLONGSIZE:
if (I16)
assert(0); // not implemented yet
goto neg_2reg;
default:
assert(0);
}
c = cat3(cl,cr,c);
forccs = 0; // flags already set by NEG
*pretregs &= ~mPSW;
}
else if ((e2 = e->E2)->Eoper == OPconst && // if rvalue is a const
el_signx32(e2) &&
// Don't evaluate e2 in register if we can use an INC or DEC
(((sz <= REGSIZE || tyfv(tyml)) &&
(op == OPaddass || op == OPminass) &&
(el_allbits(e2, 1) || el_allbits(e2, -1))
) ||
(!evalinregister(e2) && tyml != TYhptr)
)
)
{
cl = getlvalue(&cs,e1,0);
cl = cat(cl,modEA(&cs));
cs.IFL2 = FLconst;
cs.IEV2.Vint = e2->EV.Vint;
if (sz <= REGSIZE || tyfv(tyml) || opsize)
{
targ_int i = cs.IEV2.Vint;
/* Handle shortcuts. Watch out for if result has */
/* to be in flags. */
if (reghasvalue(ALLREGS,i,®) && i != 1 && i != -1 &&
!opsize)
{
cs.Iop = op1;
cs.Irm |= modregrm(0,reg,0);
}
else
{
cs.Iop = 0x81;
cs.Irm |= modregrm(0,mode,0);
switch (op)
{ case OPminass: /* convert to += */
cs.Irm ^= modregrm(0,5,0);
i = -i;
cs.IEV2.Vsize_t = i;
/* FALL-THROUGH */
case OPaddass:
if (i == 1) /* INC EA */
goto L1;
else if (i == -1) /* DEC EA */
{ cs.Irm |= modregrm(0,1,0);
L1: cs.Iop = 0xFF;
}
break;
}
}
cs.Iop ^= byte; /* for byte operations */
cs.Iflags |= opsize;
if (forccs)
cs.Iflags |= CFpsw;
else if (!I16 && cs.Iflags & CFopsize)
{
switch (op)
{ case OPorass:
case OPxorass:
cs.IEV2.Vsize_t &= 0xFFFF;
cs.Iflags &= ~CFopsize; // don't worry about MSW
break;
case OPandass:
cs.IEV2.Vsize_t |= ~0xFFFFLL;
cs.Iflags &= ~CFopsize; // don't worry about MSW
break;
case OPminass:
case OPaddass:
#if 1
if ((cs.Irm & 0xC0) == 0xC0) // EA is register
cs.Iflags &= ~CFopsize;
#else
if ((cs.Irm & 0xC0) == 0xC0 && // EA is register and
e1->Eoper == OPind) // not a register var
cs.Iflags &= ~CFopsize;
#endif
break;
default:
assert(0);
break;
}
}
// For scheduling purposes, we wish to replace:
// OP EA
// with:
// MOV reg,EA
// OP reg
// MOV EA,reg
if (forregs && sz <= REGSIZE && (cs.Irm & 0xC0) != 0xC0 &&
(config.target_cpu == TARGET_Pentium ||
config.target_cpu == TARGET_PentiumMMX) &&
config.flags4 & CFG4speed)
{ regm_t sregm;
code cs2;
// Determine which registers to use
sregm = allregs & ~idxregm(&cs);
if (byte)
sregm &= BYTEREGS;
if (sregm & forregs)
sregm &= forregs;
cr = allocreg(&sregm,®,tyml); // allocate register
cs2 = cs;
cs2.Iflags &= ~CFpsw;
cs2.Iop = 0x8B ^ byte;
code_newreg(&cs2, reg);
cr = gen(cr,&cs2); // MOV reg,EA
cs.Irm = (cs.Irm & modregrm(0,7,0)) | modregrm(3,0,reg & 7);
if (reg & 8)
cs.Irex |= REX_B;
gen(cr,&cs); // OP reg
cs2.Iop ^= 2;
gen(cr,&cs2); // MOV EA,reg
c = cat(cl,cr);
retregs = sregm;
wantres = 0;
if (e1->Ecount)
cssave(e1,retregs,EOP(e1));
}
else
{
c = gen(cl,&cs);
cs.Iflags &= ~opsize;
cs.Iflags &= ~CFpsw;
if (I16 && opsize) // if DWORD operand
cs.IEVoffset1 += 2; // compensate for wantres code
}
}
else if (sz == 2 * REGSIZE)
{ targ_uns msw;
cs.Iop = 0x81;
cs.Irm |= modregrm(0,mode,0);
c = cl;
cs.Iflags |= cflags;