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cgxmm.d
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cgxmm.d
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/**
* Compiler implementation of the
* $(LINK2 http://www.dlang.org, D programming language).
*
* Copyright: Copyright (C) 2011-2019 by The D Language Foundation, All Rights Reserved
* Authors: $(LINK2 http://www.digitalmars.com, Walter Bright)
* License: $(LINK2 http://www.boost.org/LICENSE_1_0.txt, Boost License 1.0)
* Source: $(LINK2 https://github.com/dlang/dmd/blob/master/src/dmd/backend/cgxmm.d, backend/cgxmm.d)
*/
module dmd.backend.cgxmm;
version (SCPP)
version = COMPILE;
version (MARS)
version = COMPILE;
version (COMPILE)
{
import core.stdc.stdio;
import core.stdc.stdlib;
import core.stdc.string;
import dmd.backend.cc;
import dmd.backend.cdef;
import dmd.backend.code;
import dmd.backend.code_x86;
import dmd.backend.codebuilder;
import dmd.backend.mem;
import dmd.backend.el;
import dmd.backend.global;
import dmd.backend.oper;
import dmd.backend.ty;
import dmd.backend.xmm;
version (SCPP)
import dmd.backend.exh;
version (MARS)
import dmd.backend.errors;
extern (C++):
nothrow:
int REGSIZE();
uint mask(uint m);
/*******************************************
* Is operator a store operator?
*/
bool isXMMstore(opcode_t op)
{
switch (op)
{
case STOSS: case STOAPS: case STOUPS:
case STOSD: case STOAPD: case STOUPD:
case STOD: case STOQ: case STODQA: case STODQU:
case STOHPD: case STOHPS: case STOLPD: case STOLPS: return true;
default: return false;
}
}
/*******************************************
* Move constant value into xmm register xreg.
*/
private void movxmmconst(ref CodeBuilder cdb, reg_t xreg, uint sz, targ_size_t value, regm_t flags)
{
/* Generate:
* MOV reg,value
* MOV xreg,reg
* Not so efficient. We should at least do a PXOR for 0.
*/
assert(mask(xreg) & XMMREGS);
assert(sz == 4 || sz == 8);
if (I32 && sz == 8)
{
reg_t r;
regm_t rm = ALLREGS;
allocreg(cdb,&rm,&r,TYint); // allocate scratch register
static union U { targ_size_t s; targ_long[2] l; }
U u = void;
u.l[1] = 0;
u.s = value;
targ_long *p = &u.l[0];
movregconst(cdb,r,p[0],0);
cdb.genfltreg(STO,r,0); // MOV floatreg,r
movregconst(cdb,r,p[1],0);
cdb.genfltreg(STO,r,4); // MOV floatreg+4,r
const op = xmmload(TYdouble, true);
cdb.genxmmreg(op,xreg,0,TYdouble); // MOVSD XMMreg,floatreg
}
else
{
reg_t reg;
regwithvalue(cdb,ALLREGS,value,®,(sz == 8) ? 64 : 0);
cdb.gen2(LODD,modregxrmx(3,xreg-XMM0,reg)); // MOVD xreg,reg
if (sz == 8)
code_orrex(cdb.last(), REX_W);
checkSetVex(cdb.last(), TYulong);
}
}
/***********************************************
* Do simple orthogonal operators for XMM registers.
*/
void orthxmm(ref CodeBuilder cdb, elem *e, regm_t *pretregs)
{
//printf("orthxmm(e = %p, *pretregs = %s)\n", e, regm_str(*pretregs));
elem *e1 = e.EV.E1;
elem *e2 = e.EV.E2;
// float + ifloat is not actually addition
if ((e.Eoper == OPadd || e.Eoper == OPmin) &&
((tyreal(e1.Ety) && tyimaginary(e2.Ety)) ||
(tyreal(e2.Ety) && tyimaginary(e1.Ety))))
{
regm_t retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
regm_t rretregs;
reg_t rreg;
if (tyreal(e1.Ety))
{
const reg = findreg(retregs);
rreg = findreg(retregs & ~mask(reg));
retregs = mask(reg);
rretregs = mask(rreg);
}
else
{
// Pick the second register, not the first
rreg = findreg(retregs);
rretregs = mask(rreg);
const reg = findreg(retregs & ~rretregs);
retregs = mask(reg);
}
assert(retregs && rretregs);
codelem(cdb,e1,&retregs,false); // eval left leaf
scodelem(cdb, e2, &rretregs, retregs, true); // eval right leaf
retregs |= rretregs;
if (e.Eoper == OPmin)
{
regm_t nretregs = XMMREGS & ~retregs;
reg_t sreg; // hold sign bit
const uint sz = tysize(e1.Ety);
allocreg(cdb,&nretregs,&sreg,e2.Ety);
targ_size_t signbit = 0x80000000;
if (sz == 8)
signbit = cast(targ_size_t)0x8000000000000000L;
movxmmconst(cdb,sreg, sz, signbit, 0);
getregs(cdb,nretregs);
const opcode_t xop = (sz == 8) ? XORPD : XORPS; // XORPD/S rreg,sreg
cdb.gen2(xop,modregxrmx(3,rreg-XMM0,sreg-XMM0));
}
if (retregs != *pretregs)
fixresult(cdb,e,retregs,pretregs);
return;
}
regm_t retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
const constflag = OTrel(e.Eoper);
codelem(cdb,e1,&retregs,constflag); // eval left leaf
const reg = findreg(retregs);
regm_t rretregs = XMMREGS & ~retregs;
scodelem(cdb, e2, &rretregs, retregs, true); // eval right leaf
const rreg = findreg(rretregs);
const op = xmmoperator(e1.Ety, e.Eoper);
/* We should take advantage of mem addressing modes for OP XMM,MEM
* but we do not at the moment.
*/
if (OTrel(e.Eoper))
{
cdb.gen2(op,modregxrmx(3,rreg-XMM0,reg-XMM0));
checkSetVex(cdb.last(), e1.Ety);
return;
}
getregs(cdb,retregs);
cdb.gen2(op,modregxrmx(3,reg-XMM0,rreg-XMM0));
checkSetVex(cdb.last(), e1.Ety);
if (retregs != *pretregs)
fixresult(cdb,e,retregs,pretregs);
}
/************************
* Generate code for an assignment using XMM registers.
* Params:
* opcode = store opcode to use, CMP means generate one
*/
void xmmeq(ref CodeBuilder cdb, elem *e, opcode_t op, elem *e1, elem *e2,regm_t *pretregs)
{
tym_t tymll;
int i;
code cs;
elem *e11;
bool regvar; /* true means evaluate into register variable */
regm_t varregm;
targ_int postinc;
//printf("xmmeq(e1 = %p, e2 = %p, *pretregs = %s)\n", e1, e2, regm_str(*pretregs));
tym_t tyml = tybasic(e1.Ety); /* type of lvalue */
regm_t retregs = *pretregs;
if (!(retregs & XMMREGS))
retregs = XMMREGS; // pick any XMM reg
bool aligned = xmmIsAligned(e1);
// If default, select store opcode
cs.Iop = (op == CMP) ? xmmstore(tyml, aligned) : op;
regvar = false;
varregm = 0;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
reg_t varreg;
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1.EV.Vsym,e2) && // and we can compute directly into it
varregm & XMMREGS
)
{ regvar = true;
retregs = varregm; // evaluate directly in target register
}
}
if (*pretregs & mPSW && OTleaf(e1.Eoper)) // if evaluating e1 couldn't change flags
{ // Be careful that this lines up with jmpopcode()
retregs |= mPSW;
*pretregs &= ~mPSW;
}
scodelem(cdb,e2,&retregs,0,true); // get rvalue
// Look for special case of (*p++ = ...), where p is a register variable
if (e1.Eoper == OPind &&
((e11 = e1.EV.E1).Eoper == OPpostinc || e11.Eoper == OPpostdec) &&
e11.EV.E1.Eoper == OPvar &&
e11.EV.E1.EV.Vsym.Sfl == FLreg
)
{
postinc = e11.EV.E2.EV.Vint;
if (e11.Eoper == OPpostdec)
postinc = -postinc;
getlvalue(cdb,&cs,e11,RMstore | retregs);
freenode(e11.EV.E2);
}
else
{ postinc = 0;
getlvalue(cdb,&cs,e1,RMstore | retregs); // get lvalue (cl == CNIL if regvar)
}
getregs_imm(cdb,regvar ? varregm : 0);
const reg = findreg(retregs & XMMREGS);
cs.Irm |= modregrm(0,(reg - XMM0) & 7,0);
if ((reg - XMM0) & 8)
cs.Irex |= REX_R;
// Do not generate mov from register onto itself
if (!(regvar && reg == XMM0 + ((cs.Irm & 7) | (cs.Irex & REX_B ? 8 : 0))))
{
cdb.gen(&cs); // MOV EA+offset,reg
if (op == OPeq)
checkSetVex(cdb.last(), tyml);
}
if (e1.Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
getregs_imm(cdb,retregs); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,!OTleaf(e1.Eoper)); // if lvalue is a CSE
}
fixresult(cdb,e,retregs,pretregs);
if (postinc)
{
const increg = findreg(idxregm(&cs)); // the register to increment
if (*pretregs & mPSW)
{ // Use LEA to avoid touching the flags
uint rm = cs.Irm & 7;
if (cs.Irex & REX_B)
rm |= 8;
cdb.genc1(LEA,buildModregrm(2,increg,rm),FLconst,postinc);
if (tysize(e11.EV.E1.Ety) == 8)
code_orrex(cdb.last(), REX_W);
}
else if (I64)
{
cdb.genc2(0x81,modregrmx(3,0,increg),postinc);
if (tysize(e11.EV.E1.Ety) == 8)
code_orrex(cdb.last(), REX_W);
}
else
{
if (postinc == 1)
cdb.gen1(0x40 + increg); // INC increg
else if (postinc == -cast(targ_int)1)
cdb.gen1(0x48 + increg); // DEC increg
else
{
cdb.genc2(0x81,modregrm(3,0,increg),postinc);
}
}
}
freenode(e1);
}
/********************************
* Generate code for conversion using SSE2 instructions.
*
* OPs32_d
* OPs64_d (64-bit only)
* OPu32_d (64-bit only)
* OPd_f
* OPf_d
* OPd_s32
* OPd_s64 (64-bit only)
*
*/
void xmmcnvt(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
//printf("xmmconvt: %p, %s\n", e, regm_str(*pretregs));
opcode_t op = NoOpcode;
regm_t regs;
tym_t ty;
ubyte rex = 0;
bool zx = false; // zero extend uint
/* There are no ops for integer <. float/real conversions
* but there are instructions for them. In order to use these
* try to fuse chained conversions. Be careful not to loose
* precision for real to long.
*/
elem *e1 = e.EV.E1;
switch (e.Eoper)
{
case OPd_f:
if (e1.Eoper == OPs32_d)
{ }
else if (I64 && e1.Eoper == OPs64_d)
rex = REX_W;
else if (I64 && e1.Eoper == OPu32_d)
{ rex = REX_W;
zx = true;
}
else
{ regs = XMMREGS;
op = CVTSD2SS;
ty = TYfloat;
break;
}
if (e1.Ecount)
{
regs = XMMREGS;
op = CVTSD2SS;
ty = TYfloat;
break;
}
// directly use si2ss
regs = ALLREGS;
e1 = e1.EV.E1; // fused operation
op = CVTSI2SS;
ty = TYfloat;
break;
case OPs32_d: goto Litod;
case OPs64_d: rex = REX_W; goto Litod;
case OPu32_d: rex = REX_W; zx = true; goto Litod;
Litod:
regs = ALLREGS;
op = CVTSI2SD;
ty = TYdouble;
break;
case OPd_s32: ty = TYint; goto Ldtoi;
case OPd_u32: ty = TYlong; if (I64) rex = REX_W; goto Ldtoi;
case OPd_s64: ty = TYlong; rex = REX_W; goto Ldtoi;
Ldtoi:
regs = XMMREGS;
switch (e1.Eoper)
{
case OPf_d:
if (e1.Ecount)
{
op = CVTTSD2SI;
break;
}
e1 = e1.EV.E1; // fused operation
op = CVTTSS2SI;
break;
case OPld_d:
if (e.Eoper == OPd_s64)
{
cnvt87(cdb,e,pretregs); // precision
return;
}
goto default;
default:
op = CVTTSD2SI;
break;
}
break;
case OPf_d:
regs = XMMREGS;
op = CVTSS2SD;
ty = TYdouble;
break;
default:
assert(0);
}
assert(op != NoOpcode);
codelem(cdb,e1, ®s, false);
reg_t reg = findreg(regs);
if (isXMMreg(reg))
reg -= XMM0;
else if (zx)
{ assert(I64);
getregs(cdb,regs);
genregs(cdb,0x8B,reg,reg); // MOV reg,reg to zero upper 32-bit
// Don't use x89 because that will get optimized away
code_orflag(cdb.last(),CFvolatile);
}
regm_t retregs = *pretregs;
if (tyxmmreg(ty)) // target is XMM
{ if (!(*pretregs & XMMREGS))
retregs = XMMREGS;
}
else // source is XMM
{ assert(regs & XMMREGS);
if (!(retregs & ALLREGS))
retregs = ALLREGS;
}
reg_t rreg;
allocreg(cdb,&retregs,&rreg,ty);
if (isXMMreg(rreg))
rreg -= XMM0;
cdb.gen2(op, modregxrmx(3,rreg,reg));
assert(I64 || !rex);
if (rex)
code_orrex(cdb.last(), rex);
if (*pretregs != retregs)
fixresult(cdb,e,retregs,pretregs);
}
/********************************
* Generate code for op=
*/
void xmmopass(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{ elem *e1 = e.EV.E1;
elem *e2 = e.EV.E2;
tym_t ty1 = tybasic(e1.Ety);
const sz1 = _tysize[ty1];
regm_t rretregs = XMMREGS & ~*pretregs;
if (!rretregs)
rretregs = XMMREGS;
codelem(cdb,e2,&rretregs,false); // eval right leaf
reg_t rreg = findreg(rretregs);
code cs;
regm_t retregs;
reg_t reg;
bool regvar = false;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
reg_t varreg;
regm_t varregm;
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1.EV.Vsym,e2) // and we can compute directly into it
)
{ regvar = true;
retregs = varregm;
reg = varreg; // evaluate directly in target register
getregs(cdb,retregs); // destroy these regs
}
}
if (!regvar)
{
getlvalue(cdb,&cs,e1,rretregs); // get EA
retregs = *pretregs & XMMREGS & ~rretregs;
if (!retregs)
retregs = XMMREGS & ~rretregs;
allocreg(cdb,&retregs,®,ty1);
cs.Iop = xmmload(ty1, true); // MOVSD xmm,xmm_m64
code_newreg(&cs,reg - XMM0);
cdb.gen(&cs);
checkSetVex(cdb.last(), ty1);
}
const op = xmmoperator(e1.Ety, e.Eoper);
cdb.gen2(op,modregxrmx(3,reg-XMM0,rreg-XMM0));
checkSetVex(cdb.last(), e1.Ety);
if (!regvar)
{
cs.Iop = xmmstore(ty1,true); // reverse operand order of MOVS[SD]
cdb.gen(&cs);
checkSetVex(cdb.last(), ty1);
}
if (e1.Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
getregs_imm(cdb,retregs); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,!OTleaf(e1.Eoper)); // if lvalue is a CSE
}
fixresult(cdb,e,retregs,pretregs);
freenode(e1);
}
/********************************
* Generate code for post increment and post decrement.
*/
void xmmpost(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
elem *e1 = e.EV.E1;
elem *e2 = e.EV.E2;
tym_t ty1 = tybasic(e1.Ety);
regm_t retregs;
reg_t reg;
bool regvar = false;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
reg_t varreg;
regm_t varregm;
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1.EV.Vsym,e2) // and we can compute directly into it
)
{
regvar = true;
retregs = varregm;
reg = varreg; // evaluate directly in target register
getregs(cdb,retregs); // destroy these regs
}
}
code cs;
if (!regvar)
{
getlvalue(cdb,&cs,e1,0); // get EA
retregs = XMMREGS & ~*pretregs;
if (!retregs)
retregs = XMMREGS;
allocreg(cdb,&retregs,®,ty1);
cs.Iop = xmmload(ty1, true); // MOVSD xmm,xmm_m64
code_newreg(&cs,reg - XMM0);
cdb.gen(&cs);
checkSetVex(cdb.last(), ty1);
}
// Result register
regm_t resultregs = XMMREGS & *pretregs & ~retregs;
if (!resultregs)
resultregs = XMMREGS & ~retregs;
reg_t resultreg;
allocreg(cdb,&resultregs, &resultreg, ty1);
cdb.gen2(xmmload(ty1,true),modregxrmx(3,resultreg-XMM0,reg-XMM0)); // MOVSS/D resultreg,reg
checkSetVex(cdb.last(), ty1);
regm_t rretregs = XMMREGS & ~(*pretregs | retregs | resultregs);
if (!rretregs)
rretregs = XMMREGS & ~(retregs | resultregs);
codelem(cdb,e2,&rretregs,false); // eval right leaf
const rreg = findreg(rretregs);
const op = xmmoperator(e1.Ety, e.Eoper);
cdb.gen2(op,modregxrmx(3,reg-XMM0,rreg-XMM0)); // ADD reg,rreg
checkSetVex(cdb.last(), e1.Ety);
if (!regvar)
{
cs.Iop = xmmstore(ty1,true); // reverse operand order of MOVS[SD]
cdb.gen(&cs);
checkSetVex(cdb.last(), ty1);
}
if (e1.Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
getregs_imm(cdb,retregs); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,!OTleaf(e1.Eoper)); // if lvalue is a CSE
}
fixresult(cdb,e,resultregs,pretregs);
freenode(e1);
}
/******************
* Negate operator
*/
void xmmneg(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
//printf("xmmneg()\n");
//elem_print(e);
assert(*pretregs);
tym_t tyml = tybasic(e.EV.E1.Ety);
int sz = _tysize[tyml];
regm_t retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
/* Generate:
* MOV reg,e1
* MOV rreg,signbit
* XOR reg,rreg
*/
codelem(cdb,e.EV.E1,&retregs,false);
getregs(cdb,retregs);
const reg = findreg(retregs);
regm_t rretregs = XMMREGS & ~retregs;
reg_t rreg;
allocreg(cdb,&rretregs,&rreg,tyml);
targ_size_t signbit = 0x80000000;
if (sz == 8)
signbit = cast(targ_size_t)0x8000000000000000L;
movxmmconst(cdb,rreg, sz, signbit, 0);
getregs(cdb,retregs);
const op = (sz == 8) ? XORPD : XORPS; // XORPD/S reg,rreg
cdb.gen2(op,modregxrmx(3,reg-XMM0,rreg-XMM0));
fixresult(cdb,e,retregs,pretregs);
}
/*****************************
* Get correct load operator based on type.
* It is important to use the right one even if the number of bits moved is the same,
* as there are performance consequences for using the wrong one.
* Params:
* tym = type of data to load
* aligned = for vectors, true if aligned to 16 bytes
*/
opcode_t xmmload(tym_t tym, bool aligned)
{
opcode_t op;
if (tysize(tym) == 32)
aligned = false;
switch (tybasic(tym))
{
case TYuint:
case TYint:
case TYlong:
case TYulong: op = LODD; break; // MOVD
case TYfloat:
case TYcfloat:
case TYifloat: op = LODSS; break; // MOVSS
case TYllong:
case TYullong: op = LODQ; break; // MOVQ
case TYdouble:
case TYcdouble:
case TYidouble: op = LODSD; break; // MOVSD
case TYfloat8:
case TYfloat4: op = aligned ? LODAPS : LODUPS; break; // MOVAPS / MOVUPS
case TYdouble4:
case TYdouble2: op = aligned ? LODAPD : LODUPD; break; // MOVAPD / MOVUPD
case TYschar16:
case TYuchar16:
case TYshort8:
case TYushort8:
case TYlong4:
case TYulong4:
case TYllong2:
case TYullong2:
case TYschar32:
case TYuchar32:
case TYshort16:
case TYushort16:
case TYlong8:
case TYulong8:
case TYllong4:
case TYullong4: op = aligned ? LODDQA : LODDQU; break; // MOVDQA / MOVDQU
default:
printf("tym = x%x\n", tym);
assert(0);
}
return op;
}
/*****************************
* Get correct store operator based on type.
*/
opcode_t xmmstore(tym_t tym, bool aligned)
{
opcode_t op;
switch (tybasic(tym))
{
case TYuint:
case TYint:
case TYlong:
case TYulong: op = STOD; break; // MOVD
case TYfloat:
case TYifloat: op = STOSS; break; // MOVSS
case TYllong:
case TYullong: op = STOQ; break; // MOVQ
case TYdouble:
case TYidouble:
case TYcdouble:
case TYcfloat: op = STOSD; break; // MOVSD
case TYfloat8:
case TYfloat4: op = aligned ? STOAPS : STOUPS; break; // MOVAPS / MOVUPS
case TYdouble4:
case TYdouble2: op = aligned ? STOAPD : STOUPD; break; // MOVAPD / MOVUPD
case TYschar16:
case TYuchar16:
case TYshort8:
case TYushort8:
case TYlong4:
case TYulong4:
case TYllong2:
case TYullong2:
case TYschar32:
case TYuchar32:
case TYshort16:
case TYushort16:
case TYlong8:
case TYulong8:
case TYllong4:
case TYullong4: op = aligned ? STODQA : STODQU; break; // MOVDQA / MOVDQU
default:
printf("tym = 0x%x\n", tym);
assert(0);
}
return op;
}
/************************************
* Get correct XMM operator based on type and operator.
*/
private opcode_t xmmoperator(tym_t tym, OPER oper)
{
tym = tybasic(tym);
opcode_t op;
switch (oper)
{
case OPadd:
case OPaddass:
case OPpostinc:
switch (tym)
{
case TYfloat:
case TYifloat: op = ADDSS; break;
case TYdouble:
case TYidouble: op = ADDSD; break;
// SIMD vector types
case TYfloat8:
case TYfloat4: op = ADDPS; break;
case TYdouble4:
case TYdouble2: op = ADDPD; break;
case TYschar32:
case TYuchar32:
case TYschar16:
case TYuchar16: op = PADDB; break;
case TYshort16:
case TYushort16:
case TYshort8:
case TYushort8: op = PADDW; break;
case TYlong8:
case TYulong8:
case TYlong4:
case TYulong4: op = PADDD; break;
case TYllong4:
case TYullong4:
case TYllong2:
case TYullong2: op = PADDQ; break;
default:
printf("tym = x%x\n", tym);
assert(0);
}
break;
case OPmin:
case OPminass:
case OPpostdec:
switch (tym)
{
case TYfloat:
case TYifloat: op = SUBSS; break;
case TYdouble:
case TYidouble: op = SUBSD; break;
// SIMD vector types
case TYfloat8:
case TYfloat4: op = SUBPS; break;
case TYdouble4:
case TYdouble2: op = SUBPD; break;
case TYschar32:
case TYuchar32:
case TYschar16:
case TYuchar16: op = PSUBB; break;
case TYshort16:
case TYushort16:
case TYshort8:
case TYushort8: op = PSUBW; break;
case TYlong8:
case TYulong8:
case TYlong4:
case TYulong4: op = PSUBD; break;
case TYllong4:
case TYullong4:
case TYllong2:
case TYullong2: op = PSUBQ; break;
default: assert(0);
}
break;
case OPmul:
case OPmulass:
switch (tym)
{
case TYfloat:
case TYifloat: op = MULSS; break;
case TYdouble:
case TYidouble: op = MULSD; break;
// SIMD vector types
case TYfloat8:
case TYfloat4: op = MULPS; break;
case TYdouble4:
case TYdouble2: op = MULPD; break;
case TYshort16:
case TYushort16:
case TYshort8:
case TYushort8: op = PMULLW; break;
case TYlong8:
case TYulong8:
case TYlong4:
case TYulong4: op = PMULLD; break;
default: assert(0);
}
break;
case OPdiv:
case OPdivass:
switch (tym)
{
case TYfloat:
case TYifloat: op = DIVSS; break;
case TYdouble:
case TYidouble: op = DIVSD; break;
// SIMD vector types
case TYfloat8:
case TYfloat4: op = DIVPS; break;
case TYdouble4:
case TYdouble2: op = DIVPD; break;
default: assert(0);
}
break;
case OPor:
case OPorass:
switch (tym)
{
// SIMD vector types
case TYschar16:
case TYuchar16:
case TYshort8:
case TYushort8:
case TYlong4:
case TYulong4:
case TYllong2:
case TYullong2:
case TYschar32:
case TYuchar32:
case TYshort16:
case TYushort16:
case TYlong8:
case TYulong8:
case TYllong4:
case TYullong4: op = POR; break;
default: assert(0);
}
break;
case OPand:
case OPandass:
switch (tym)
{
// SIMD vector types
case TYschar16:
case TYuchar16:
case TYshort8:
case TYushort8:
case TYlong4:
case TYulong4:
case TYllong2:
case TYullong2:
case TYschar32:
case TYuchar32:
case TYshort16:
case TYushort16:
case TYlong8:
case TYulong8:
case TYllong4:
case TYullong4: op = PAND; break;
default: assert(0);
}
break;
case OPxor:
case OPxorass:
switch (tym)
{
// SIMD vector types
case TYschar16:
case TYuchar16:
case TYshort8:
case TYushort8:
case TYlong4:
case TYulong4:
case TYllong2:
case TYullong2:
case TYschar32:
case TYuchar32:
case TYshort16:
case TYushort16:
case TYlong8:
case TYulong8:
case TYllong4:
case TYullong4: op = PXOR; break;
default: assert(0);
}
break;
case OPlt:
case OPle:
case OPgt:
case OPge:
case OPne:
case OPeqeq:
case OPunord: /* !<>= */
case OPlg: /* <> */
case OPleg: /* <>= */
case OPule: /* !> */
case OPul: /* !>= */
case OPuge: /* !< */
case OPug: /* !<= */
case OPue: /* !<> */
case OPngt:
case OPnge:
case OPnlt:
case OPnle:
case OPord:
case OPnlg: