/
cod4.d
4114 lines (3771 loc) · 131 KB
/
cod4.d
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/**
* Compiler implementation of the
* $(LINK2 http://www.dlang.org, D programming language).
*
* Copyright: Copyright (C) 1985-1998 by Symantec
* Copyright (C) 2000-2020 by The D Language Foundation, All Rights Reserved
* Authors: $(LINK2 http://www.digitalmars.com, Walter Bright)
* License: $(LINK2 http://www.boost.org/LICENSE_1_0.txt, Boost License 1.0)
* Source: $(LINK2 https://github.com/dlang/dmd/blob/master/src/dmd/backend/cod4.d, backend/cod4.d)
*/
module dmd.backend.cod4;
version (SCPP)
version = COMPILE;
version (MARS)
version = COMPILE;
version (COMPILE)
{
import core.stdc.stdio;
import core.stdc.stdlib;
import core.stdc.string;
import dmd.backend.cc;
import dmd.backend.cdef;
import dmd.backend.code;
import dmd.backend.code_x86;
import dmd.backend.codebuilder;
import dmd.backend.mem;
import dmd.backend.el;
import dmd.backend.global;
import dmd.backend.oper;
import dmd.backend.ty;
import dmd.backend.evalu8 : el_toldoubled;
import dmd.backend.xmm;
extern (C++):
nothrow:
int REGSIZE();
extern __gshared CGstate cgstate;
extern __gshared bool[FLMAX] datafl;
private extern (D) uint mask(uint m) { return 1 << m; }
/* AX,CX,DX,BX */
__gshared const reg_t[4] dblreg = [ BX,DX,NOREG,CX ];
/*******************************
* Return number of times symbol s appears in tree e.
*/
private int intree(Symbol *s,elem *e)
{
if (!OTleaf(e.Eoper))
return intree(s,e.EV.E1) + (OTbinary(e.Eoper) ? intree(s,e.EV.E2) : 0);
return e.Eoper == OPvar && e.EV.Vsym == s;
}
/***********************************
* Determine if expression e can be evaluated directly into register
* variable s.
* Have to be careful about things like x=x+x+x, and x=a+x.
* Returns:
* !=0 can
* 0 can't
*/
int doinreg(Symbol *s, elem *e)
{
int in_ = 0;
OPER op;
L1:
op = e.Eoper;
if (op == OPind ||
OTcall(op) ||
OTleaf(op) ||
(in_ = intree(s,e)) == 0 ||
(OTunary(op) && OTleaf(e.EV.E1.Eoper))
)
return 1;
if (in_ == 1)
{
switch (op)
{
case OPadd:
case OPmin:
case OPand:
case OPor:
case OPxor:
case OPshl:
case OPmul:
if (!intree(s,e.EV.E2))
{
e = e.EV.E1;
goto L1;
}
break;
default:
break;
}
}
return 0;
}
/****************************
* Return code for saving common subexpressions if EA
* turns out to be a register.
* This is called just before modifying an EA.
*/
void modEA(ref CodeBuilder cdb,code *c)
{
if ((c.Irm & 0xC0) == 0xC0) // addressing mode refers to a register
{
reg_t reg = c.Irm & 7;
if (c.Irex & REX_B)
{ reg |= 8;
assert(I64);
}
getregs(cdb,mask(reg));
}
}
static if (TARGET_WINDOS)
{
// This code is for CPUs that do not support the 8087
/****************************
* Gen code for op= for doubles.
*/
private void opassdbl(ref CodeBuilder cdb,elem *e,regm_t *pretregs,OPER op)
{
static immutable uint[OPdivass - OPpostinc + 1] clibtab =
/* OPpostinc,OPpostdec,OPeq,OPaddass,OPminass,OPmulass,OPdivass */
[ CLIB.dadd, CLIB.dsub, cast(uint)-1, CLIB.dadd,CLIB.dsub,CLIB.dmul,CLIB.ddiv ];
if (config.inline8087)
{
opass87(cdb,e,pretregs);
return;
}
code cs;
regm_t retregs2,retregs,idxregs;
uint clib = clibtab[op - OPpostinc];
elem *e1 = e.EV.E1;
tym_t tym = tybasic(e1.Ety);
getlvalue(cdb,&cs,e1,DOUBLEREGS | mBX | mCX);
if (tym == TYfloat)
{
clib += CLIB.fadd - CLIB.dadd; /* convert to float operation */
// Load EA into FLOATREGS
getregs(cdb,FLOATREGS);
cs.Iop = 0x8B;
cs.Irm |= modregrm(0,AX,0);
cdb.gen(&cs);
if (!I32)
{
cs.Irm |= modregrm(0,DX,0);
getlvalue_msw(&cs);
cdb.gen(&cs);
getlvalue_lsw(&cs);
}
retregs2 = FLOATREGS2;
idxregs = FLOATREGS | idxregm(&cs);
retregs = FLOATREGS;
}
else
{
if (I32)
{
// Load EA into DOUBLEREGS
getregs(cdb,DOUBLEREGS_32);
cs.Iop = 0x8B;
cs.Irm |= modregrm(0,AX,0);
cdb.gen(&cs);
cs.Irm |= modregrm(0,DX,0);
getlvalue_msw(&cs);
cdb.gen(&cs);
getlvalue_lsw(&cs);
retregs2 = DOUBLEREGS2_32;
idxregs = DOUBLEREGS_32 | idxregm(&cs);
}
else
{
// Push EA onto stack
cs.Iop = 0xFF;
cs.Irm |= modregrm(0,6,0);
cs.IEV1.Voffset += DOUBLESIZE - REGSIZE;
cdb.gen(&cs);
getlvalue_lsw(&cs);
cdb.gen(&cs);
getlvalue_lsw(&cs);
cdb.gen(&cs);
getlvalue_lsw(&cs);
cdb.gen(&cs);
stackpush += DOUBLESIZE;
retregs2 = DOUBLEREGS_16;
idxregs = idxregm(&cs);
}
retregs = DOUBLEREGS;
}
if ((cs.Iflags & CFSEG) == CFes)
idxregs |= mES;
cgstate.stackclean++;
scodelem(cdb,e.EV.E2,&retregs2,idxregs,false);
cgstate.stackclean--;
callclib(cdb,e,clib,&retregs,0);
if (e1.Ecount)
cssave(e1,retregs,!OTleaf(e1.Eoper)); // if lvalue is a CSE
freenode(e1);
cs.Iop = 0x89; // MOV EA,DOUBLEREGS
fltregs(cdb,&cs,tym);
fixresult(cdb,e,retregs,pretregs);
}
/****************************
* Gen code for OPnegass for doubles.
*/
private void opnegassdbl(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
if (config.inline8087)
{
cdnegass87(cdb,e,pretregs);
return;
}
elem *e1 = e.EV.E1;
tym_t tym = tybasic(e1.Ety);
int sz = _tysize[tym];
code cs;
getlvalue(cdb,&cs,e1,*pretregs ? DOUBLEREGS | mBX | mCX : 0);
modEA(cdb,&cs);
cs.Irm |= modregrm(0,6,0);
cs.Iop = 0x80;
cs.IEV1.Voffset += sz - 1;
cs.IFL2 = FLconst;
cs.IEV2.Vuns = 0x80;
cdb.gen(&cs); // XOR 7[EA],0x80
if (tycomplex(tym))
{
cs.IEV1.Voffset -= sz / 2;
cdb.gen(&cs); // XOR 7[EA],0x80
}
regm_t retregs;
if (*pretregs || e1.Ecount)
{
cs.IEV1.Voffset -= sz - 1;
if (tym == TYfloat)
{
// Load EA into FLOATREGS
getregs(cdb,FLOATREGS);
cs.Iop = 0x8B;
NEWREG(cs.Irm, AX);
cdb.gen(&cs);
if (!I32)
{
NEWREG(cs.Irm, DX);
getlvalue_msw(&cs);
cdb.gen(&cs);
getlvalue_lsw(&cs);
}
retregs = FLOATREGS;
}
else
{
if (I32)
{
// Load EA into DOUBLEREGS
getregs(cdb,DOUBLEREGS_32);
cs.Iop = 0x8B;
cs.Irm &= ~cast(uint)modregrm(0,7,0);
cs.Irm |= modregrm(0,AX,0);
cdb.gen(&cs);
cs.Irm |= modregrm(0,DX,0);
getlvalue_msw(&cs);
cdb.gen(&cs);
getlvalue_lsw(&cs);
}
else
{
static if (1)
{
cs.Iop = 0x8B;
fltregs(cdb,&cs,TYdouble); // MOV DOUBLEREGS, EA
}
else
{
// Push EA onto stack
cs.Iop = 0xFF;
cs.Irm |= modregrm(0,6,0);
cs.IEV1.Voffset += DOUBLESIZE - REGSIZE;
cdb.gen(&cs);
cs.IEV1.Voffset -= REGSIZE;
cdb.gen(&cs);
cs.IEV1.Voffset -= REGSIZE;
cdb.gen(&cs);
cs.IEV1.Voffset -= REGSIZE;
cdb.gen(&cs);
stackpush += DOUBLESIZE;
}
}
retregs = DOUBLEREGS;
}
if (e1.Ecount)
cssave(e1,retregs,!OTleaf(e1.Eoper)); /* if lvalue is a CSE */
}
else
{
retregs = 0;
assert(e1.Ecount == 0);
}
freenode(e1);
fixresult(cdb,e,retregs,pretregs);
}
}
/************************
* Generate code for an assignment.
*/
void cdeq(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
tym_t tymll;
reg_t reg;
code cs;
elem *e11;
bool regvar; // true means evaluate into register variable
regm_t varregm;
reg_t varreg;
targ_int postinc;
//printf("cdeq(e = %p, *pretregs = %s)\n", e, regm_str(*pretregs));
elem *e1 = e.EV.E1;
elem *e2 = e.EV.E2;
int e2oper = e2.Eoper;
tym_t tyml = tybasic(e1.Ety); // type of lvalue
regm_t retregs = *pretregs;
if (tyxmmreg(tyml) && config.fpxmmregs)
{
xmmeq(cdb, e, CMP, e1, e2, pretregs);
return;
}
if (tyfloating(tyml) && config.inline8087)
{
if (tycomplex(tyml))
{
complex_eq87(cdb, e, pretregs);
return;
}
if (!(retregs == 0 &&
(e2oper == OPconst || e2oper == OPvar || e2oper == OPind))
)
{
eq87(cdb,e,pretregs);
return;
}
if (config.target_cpu >= TARGET_PentiumPro &&
(e2oper == OPvar || e2oper == OPind)
)
{
eq87(cdb,e,pretregs);
return;
}
if (tyml == TYldouble || tyml == TYildouble)
{
eq87(cdb,e,pretregs);
return;
}
}
uint sz = _tysize[tyml]; // # of bytes to transfer
assert(cast(int)sz > 0);
if (retregs == 0) // if no return value
{
int fl;
/* If registers are tight, and we might need them for the lvalue,
* prefer to not use them for the rvalue
*/
bool plenty = true;
if (e1.Eoper == OPind)
{
/* Will need 1 register for evaluation, +2 registers for
* e1's addressing mode
*/
regm_t m = allregs & ~regcon.mvar; // mask of non-register variables
m &= m - 1; // clear least significant bit
m &= m - 1; // clear least significant bit
plenty = m != 0; // at least 3 registers
}
if ((e2oper == OPconst || // if rvalue is a constant
e2oper == OPrelconst &&
!(I64 && (config.flags3 & CFG3pic || config.exe == EX_WIN64)) &&
((fl = el_fl(e2)) == FLdata ||
fl==FLudata || fl == FLextern)
&& !(e2.EV.Vsym.ty() & mTYcs)
) &&
!(evalinregister(e2) && plenty) &&
!e1.Ecount) // and no CSE headaches
{
// Look for special case of (*p++ = ...), where p is a register variable
if (e1.Eoper == OPind &&
((e11 = e1.EV.E1).Eoper == OPpostinc || e11.Eoper == OPpostdec) &&
e11.EV.E1.Eoper == OPvar &&
e11.EV.E1.EV.Vsym.Sfl == FLreg &&
(!I16 || e11.EV.E1.EV.Vsym.Sregm & IDXREGS)
)
{
Symbol *s = e11.EV.E1.EV.Vsym;
if (s.Sclass == SCfastpar || s.Sclass == SCshadowreg)
{
regcon.params &= ~s.Spregm();
}
postinc = e11.EV.E2.EV.Vint;
if (e11.Eoper == OPpostdec)
postinc = -postinc;
getlvalue(cdb,&cs,e1,RMstore);
freenode(e11.EV.E2);
}
else
{
postinc = 0;
getlvalue(cdb,&cs,e1,RMstore);
if (e2oper == OPconst &&
config.flags4 & CFG4speed &&
(config.target_cpu == TARGET_Pentium ||
config.target_cpu == TARGET_PentiumMMX) &&
(cs.Irm & 0xC0) == 0x80
)
{
if (I64 && sz == 8 && e2.EV.Vpointer)
{
// MOV reg,imm64
// MOV EA,reg
regm_t rregm = allregs & ~idxregm(&cs);
reg_t regx;
regwithvalue(cdb,rregm,e2.EV.Vpointer,®x,64);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,regx & 7,0);
if (regx & 8)
cs.Irex |= REX_R;
cdb.gen(&cs);
freenode(e2);
goto Lp;
}
if ((sz == REGSIZE || (I64 && sz == 4)) && e2.EV.Vint)
{
// MOV reg,imm
// MOV EA,reg
regm_t rregm = allregs & ~idxregm(&cs);
reg_t regx;
regwithvalue(cdb,rregm,e2.EV.Vint,®x,0);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,regx & 7,0);
if (regx & 8)
cs.Irex |= REX_R;
cdb.gen(&cs);
freenode(e2);
goto Lp;
}
if (sz == 2 * REGSIZE && e2.EV.Vllong == 0)
{
// MOV reg,imm
// MOV EA,reg
// MOV EA+2,reg
regm_t rregm = getscratch() & ~idxregm(&cs);
if (rregm)
{
reg_t regx;
regwithvalue(cdb,rregm,e2.EV.Vint,®x,0);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,regx,0);
cdb.gen(&cs);
getlvalue_msw(&cs);
cdb.gen(&cs);
freenode(e2);
goto Lp;
}
}
}
}
// If loading result into a register
if ((cs.Irm & 0xC0) == 0xC0)
{
modEA(cdb,&cs);
if (sz == 2 * REGSIZE && cs.IFL1 == FLreg)
getregs(cdb,cs.IEV1.Vsym.Sregm);
}
cs.Iop = (sz == 1) ? 0xC6 : 0xC7;
if (e2oper == OPrelconst)
{
cs.IEV2.Voffset = e2.EV.Voffset;
cs.IFL2 = cast(ubyte)fl;
cs.IEV2.Vsym = e2.EV.Vsym;
cs.Iflags |= CFoff;
cdb.gen(&cs); // MOV EA,&variable
if (I64 && sz == 8)
code_orrex(cdb.last(), REX_W);
if (sz > REGSIZE)
{
cs.Iop = 0x8C;
getlvalue_msw(&cs);
cs.Irm |= modregrm(0,3,0);
cdb.gen(&cs); // MOV EA+2,DS
}
}
else
{
assert(e2oper == OPconst);
cs.IFL2 = FLconst;
targ_size_t *p = cast(targ_size_t *) &(e2.EV);
cs.IEV2.Vsize_t = *p;
// Look for loading a register variable
if ((cs.Irm & 0xC0) == 0xC0)
{
reg_t regx = cs.Irm & 7;
if (cs.Irex & REX_B)
regx |= 8;
if (I64 && sz == 8)
movregconst(cdb,regx,*p,64);
else
movregconst(cdb,regx,*p,1 ^ (cs.Iop & 1));
if (sz == 2 * REGSIZE)
{ getlvalue_msw(&cs);
if (REGSIZE == 2)
movregconst(cdb,cs.Irm & 7,(cast(ushort *)p)[1],0);
else if (REGSIZE == 4)
movregconst(cdb,cs.Irm & 7,(cast(uint *)p)[1],0);
else if (REGSIZE == 8)
movregconst(cdb,cs.Irm & 7,p[1],0);
else
assert(0);
}
}
else if (I64 && sz == 8 && *p >= 0x80000000)
{ // Use 64 bit MOV, as the 32 bit one gets sign extended
// MOV reg,imm64
// MOV EA,reg
regm_t rregm = allregs & ~idxregm(&cs);
reg_t regx;
regwithvalue(cdb,rregm,*p,®x,64);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,regx & 7,0);
if (regx & 8)
cs.Irex |= REX_R;
cdb.gen(&cs);
}
else
{
int off = sz;
do
{ int regsize = REGSIZE;
if (off >= 4 && I16 && config.target_cpu >= TARGET_80386)
{
regsize = 4;
cs.Iflags |= CFopsize; // use opsize to do 32 bit operation
}
else if (I64 && sz == 16 && *p >= 0x80000000)
{
regm_t rregm = allregs & ~idxregm(&cs);
reg_t regx;
regwithvalue(cdb,rregm,*p,®x,64);
cs.Iop = 0x89;
cs.Irm |= modregrm(0,regx & 7,0);
if (regx & 8)
cs.Irex |= REX_R;
}
else
{
regm_t retregsx = (sz == 1) ? BYTEREGS : allregs;
reg_t regx;
if (reghasvalue(retregsx,*p,®x))
{
cs.Iop = (cs.Iop & 1) | 0x88;
cs.Irm |= modregrm(0,regx & 7,0); // MOV EA,regx
if (regx & 8)
cs.Irex |= REX_R;
if (I64 && sz == 1 && regx >= 4)
cs.Irex |= REX;
}
if (!I16 && off == 2) // if 16 bit operand
cs.Iflags |= CFopsize;
if (I64 && sz == 8)
cs.Irex |= REX_W;
}
cdb.gen(&cs); // MOV EA,const
p = cast(targ_size_t *)(cast(char *) p + regsize);
cs.Iop = (cs.Iop & 1) | 0xC6;
cs.Irm &= cast(ubyte)~cast(int)modregrm(0,7,0);
cs.Irex &= ~REX_R;
cs.IEV1.Voffset += regsize;
cs.IEV2.Vint = cast(int)*p;
off -= regsize;
} while (off > 0);
}
}
freenode(e2);
goto Lp;
}
retregs = allregs; // pick a reg, any reg
if (sz == 2 * REGSIZE)
retregs &= ~mBP; // BP cannot be used for register pair
}
if (retregs == mPSW)
{
retregs = allregs;
if (sz == 2 * REGSIZE)
retregs &= ~mBP; // BP cannot be used for register pair
}
cs.Iop = 0x89;
if (sz == 1) // must have byte regs
{
cs.Iop = 0x88;
retregs &= BYTEREGS;
if (!retregs)
retregs = BYTEREGS;
}
else if (retregs & mES &&
(
(e1.Eoper == OPind &&
((tymll = tybasic(e1.EV.E1.Ety)) == TYfptr || tymll == TYhptr)) ||
(e1.Eoper == OPvar && e1.EV.Vsym.Sfl == FLfardata)
)
)
// getlvalue() needs ES, so we can't return it
retregs = allregs; // no conflicts with ES
else if (tyml == TYdouble || tyml == TYdouble_alias || retregs & mST0)
retregs = DOUBLEREGS;
regvar = false;
varregm = 0;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1.EV.Vsym,e2) && // and we can compute directly into it
!(sz == 1 && e1.EV.Voffset == 1)
)
{
regvar = true;
retregs = varregm;
reg = varreg; // evaluate directly in target register
if (tysize(e1.Ety) == REGSIZE &&
tysize(e1.EV.Vsym.Stype.Tty) == 2 * REGSIZE)
{
if (e1.EV.Voffset)
retregs &= mMSW;
else
retregs &= mLSW;
reg = findreg(retregs);
}
}
}
if (*pretregs & mPSW && OTleaf(e1.Eoper)) // if evaluating e1 couldn't change flags
{ // Be careful that this lines up with jmpopcode()
retregs |= mPSW;
*pretregs &= ~mPSW;
}
scodelem(cdb,e2,&retregs,0,true); // get rvalue
// Look for special case of (*p++ = ...), where p is a register variable
if (e1.Eoper == OPind &&
((e11 = e1.EV.E1).Eoper == OPpostinc || e11.Eoper == OPpostdec) &&
e11.EV.E1.Eoper == OPvar &&
e11.EV.E1.EV.Vsym.Sfl == FLreg &&
(!I16 || e11.EV.E1.EV.Vsym.Sregm & IDXREGS)
)
{
Symbol *s = e11.EV.E1.EV.Vsym;
if (s.Sclass == SCfastpar || s.Sclass == SCshadowreg)
{
regcon.params &= ~s.Spregm();
}
postinc = e11.EV.E2.EV.Vint;
if (e11.Eoper == OPpostdec)
postinc = -postinc;
getlvalue(cdb,&cs,e1,RMstore | retregs);
freenode(e11.EV.E2);
}
else
{
postinc = 0;
getlvalue(cdb,&cs,e1,RMstore | retregs); // get lvalue (cl == null if regvar)
}
getregs(cdb,varregm);
assert(!(retregs & mES && (cs.Iflags & CFSEG) == CFes));
if ((tyml == TYfptr || tyml == TYhptr) && retregs & mES)
{
reg = findreglsw(retregs);
cs.Irm |= modregrm(0,reg,0);
cdb.gen(&cs); // MOV EA,reg
getlvalue_msw(&cs); // point to where segment goes
cs.Iop = 0x8C;
NEWREG(cs.Irm,0);
cdb.gen(&cs); // MOV EA+2,ES
}
else
{
if (!I16)
{
reg = findreg(retregs &
((sz > REGSIZE) ? mBP | mLSW : mBP | ALLREGS));
cs.Irm |= modregrm(0,reg & 7,0);
if (reg & 8)
cs.Irex |= REX_R;
for (; true; sz -= REGSIZE)
{
// Do not generate mov from register onto itself
if (regvar && reg == ((cs.Irm & 7) | (cs.Irex & REX_B ? 8 : 0)))
break;
if (sz == 2) // if 16 bit operand
cs.Iflags |= CFopsize;
else if (sz == 1 && reg >= 4)
cs.Irex |= REX;
cdb.gen(&cs); // MOV EA+offset,reg
if (sz <= REGSIZE)
break;
getlvalue_msw(&cs);
reg = findregmsw(retregs);
code_newreg(&cs, reg);
}
}
else
{
if (sz > REGSIZE)
cs.IEV1.Voffset += sz - REGSIZE; // 0,2,6
reg = findreg(retregs &
(sz > REGSIZE ? mMSW : ALLREGS));
if (tyml == TYdouble || tyml == TYdouble_alias)
reg = AX;
cs.Irm |= modregrm(0,reg,0);
// Do not generate mov from register onto itself
if (!regvar || reg != (cs.Irm & 7))
for (; true; sz -= REGSIZE) // 1,2,4
{
cdb.gen(&cs); // MOV EA+offset,reg
if (sz <= REGSIZE)
break;
cs.IEV1.Voffset -= REGSIZE;
if (tyml == TYdouble || tyml == TYdouble_alias)
reg = dblreg[reg];
else
reg = findreglsw(retregs);
NEWREG(cs.Irm,reg);
}
}
}
if (e1.Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
getregs_imm(cdb,retregs); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,!OTleaf(e1.Eoper)); // if lvalue is a CSE
}
fixresult(cdb,e,retregs,pretregs);
Lp:
if (postinc)
{
reg_t ireg = findreg(idxregm(&cs));
if (*pretregs & mPSW)
{ // Use LEA to avoid touching the flags
uint rm = cs.Irm & 7;
if (cs.Irex & REX_B)
rm |= 8;
cdb.genc1(LEA,buildModregrm(2,ireg,rm),FLconst,postinc);
if (tysize(e11.EV.E1.Ety) == 8)
code_orrex(cdb.last(), REX_W);
}
else if (I64)
{
cdb.genc2(0x81,modregrmx(3,0,ireg),postinc);
if (tysize(e11.EV.E1.Ety) == 8)
code_orrex(cdb.last(), REX_W);
}
else
{
if (postinc == 1)
cdb.gen1(0x40 + ireg); // INC ireg
else if (postinc == -cast(targ_int)1)
cdb.gen1(0x48 + ireg); // DEC ireg
else
{
cdb.genc2(0x81,modregrm(3,0,ireg),postinc);
}
}
}
freenode(e1);
}
/************************
* Generate code for += -= &= |= ^= negass
*/
void cdaddass(ref CodeBuilder cdb,elem *e,regm_t *pretregs)
{
//printf("cdaddass(e=%p, *pretregs = %s)\n",e,regm_str(*pretregs));
OPER op = e.Eoper;
regm_t retregs = 0;
uint reverse = 0;
elem *e1 = e.EV.E1;
tym_t tyml = tybasic(e1.Ety); // type of lvalue
int sz = _tysize[tyml];
int isbyte = (sz == 1); // 1 for byte operation, else 0
// See if evaluate in XMM registers
if (config.fpxmmregs && tyxmmreg(tyml) && op != OPnegass && !(*pretregs & mST0))
{
xmmopass(cdb,e,pretregs);
return;
}
if (tyfloating(tyml))
{
static if (TARGET_LINUX || TARGET_OSX || TARGET_FREEBSD || TARGET_OPENBSD || TARGET_DRAGONFLYBSD || TARGET_SOLARIS)
{
if (op == OPnegass)
cdnegass87(cdb,e,pretregs);
else
opass87(cdb,e,pretregs);
}
else
{
if (op == OPnegass)
opnegassdbl(cdb,e,pretregs);
else
opassdbl(cdb,e,pretregs,op);
}
return;
}
uint opsize = (I16 && tylong(tyml) && config.target_cpu >= TARGET_80386)
? CFopsize : 0;
uint cflags = 0;
regm_t forccs = *pretregs & mPSW; // return result in flags
regm_t forregs = *pretregs & ~mPSW; // return result in regs
// true if we want the result in a register
uint wantres = forregs || (e1.Ecount && !OTleaf(e1.Eoper));
reg_t reg;
uint op1,op2,mode;
code cs;
elem *e2;
regm_t varregm;
reg_t varreg;
uint jop;
switch (op) // select instruction opcodes
{
case OPpostinc: op = OPaddass; // i++ => +=
goto case OPaddass;
case OPaddass: op1 = 0x01; op2 = 0x11;
cflags = CFpsw;
mode = 0; break; // ADD, ADC
case OPpostdec: op = OPminass; // i-- => -=
goto case OPminass;
case OPminass: op1 = 0x29; op2 = 0x19;
cflags = CFpsw;
mode = 5; break; // SUB, SBC
case OPandass: op1 = op2 = 0x21;
mode = 4; break; // AND, AND
case OPorass: op1 = op2 = 0x09;
mode = 1; break; // OR , OR
case OPxorass: op1 = op2 = 0x31;
mode = 6; break; // XOR, XOR
case OPnegass: op1 = 0xF7; // NEG
break;
default:
assert(0);
}
op1 ^= isbyte; // bit 0 is 0 for byte operation
if (op == OPnegass)
{
getlvalue(cdb,&cs,e1,0);
modEA(cdb,&cs);
cs.Irm |= modregrm(0,3,0);
cs.Iop = op1;
switch (_tysize[tyml])
{
case CHARSIZE:
cdb.gen(&cs);
break;
case SHORTSIZE:
cdb.gen(&cs);
if (!I16 && *pretregs & mPSW)
cdb.last().Iflags |= CFopsize | CFpsw;
break;
case LONGSIZE:
if (!I16 || opsize)
{ cdb.gen(&cs);
cdb.last().Iflags |= opsize;
break;
}
neg_2reg:
getlvalue_msw(&cs);
cdb.gen(&cs); // NEG EA+2
getlvalue_lsw(&cs);
cdb.gen(&cs); // NEG EA
code_orflag(cdb.last(),CFpsw);
cs.Iop = 0x81;
getlvalue_msw(&cs);
cs.IFL2 = FLconst;
cs.IEV2.Vuns = 0;
cdb.gen(&cs); // SBB EA+2,0
break;
case LLONGSIZE:
if (I16)
assert(0); // not implemented yet
if (I32)
goto neg_2reg;
cdb.gen(&cs);
break;
default:
assert(0);
}
forccs = 0; // flags already set by NEG
*pretregs &= ~mPSW;
}
else if ((e2 = e.EV.E2).Eoper == OPconst && // if rvalue is a const
el_signx32(e2) &&
// Don't evaluate e2 in register if we can use an INC or DEC
(((sz <= REGSIZE || tyfv(tyml)) &&
(op == OPaddass || op == OPminass) &&
(el_allbits(e2, 1) || el_allbits(e2, -1))
) ||
(!evalinregister(e2)
&& tyml != TYhptr
)
)
)
{
getlvalue(cdb,&cs,e1,0);
modEA(cdb,&cs);
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = e2.EV.Vint;
if (sz <= REGSIZE || tyfv(tyml) || opsize)
{
targ_int i = cs.IEV2.Vint;
// Handle shortcuts. Watch out for if result has
// to be in flags.
if (reghasvalue(isbyte ? BYTEREGS : ALLREGS,i,®) && i != 1 && i != -1 &&
!opsize)
{