DISCLAIMER Everything you see here is the result of the work of an amateur hobbyist. I had no knowledge in any required field for this project when I started, so I offer no guarantee that, if you replicate my work, you may end burning up you Commodore, your fingertips, or your whole house. So far, no Commodore equipment (or fingertips, or whole house) have been permanently damaged in any way. But I can't promise to keep it that way.
The 74HCT6526 is a very amateur attempt at building a MOS6526 replica using discrete logic. This repo is publicly shared just for educational purposes, and I can offer no guarantee on the correct behaviour of this implementation. So far, it's working great for me, but I can't promise anything.
As of v0.2.2, the 74HCT6526 is extremely cycle accurate when compared to a real 6526. Some VICE test still fail on edge cases, but it has been tested against multiple games with very satisfactory results.
Work on the 74HCT6526 began in the summer of 2018. I was so impressed by other attempts at replicating Commodore chips, that I wanted to give it myself a try. I chose the CIA, as it wasn't replicated back then, even though it seemed the simplest chip. I had no previous knowledge in electronics, only some lessons back in college more than 20 years ago.
Please visit http://forum.6502.org/viewtopic.php?f=4&t=5593 for more information
74HCT6526 is released under the following versioning scheme:
MAJOR.MINOR.REVISION
For a stack to work properly, is mandatory that all boards share the same MAJOR.MINOR versión. Any change than renders a board incompatible with the previous releases triggers a new MINOR version. If a version only includes fixes, but does not alter the buses, it's only a new revision. There may be some cases where boards with different MAJOR.MINOR version can actually work together, but this is not something I can guarantee or predict. A deep look at the schematics to understand the differences between releases is needed to actually confirm this.
Under the current scheme, I don't think I'll ever need a new MAJOR version, but it is nice to have it there, just in case.
In the upgrades folder, there's a guide for each version/board pair, with instructions to upgrade the board up until the latest version. You'll see theres no file for the latest version (As there's no upgrade path for it).
Whenever a new release is published, upgrade path for the now second-oldest release will by published.
WARNING! I offer no guarantee on anything on this project, but, specially on the upgrades part.
All boards are tested against JLCPCB and PCBWAY capabilities. For PCBWAY, there is no increase in cost compared to the standard 4 layer board.
- v0.1.0 First production run. Only includes B0 (DDR and PORTs)
- v0.1.0a First production run for B1. (TIMERA and CREGA)
- v0.1.1 Second production run for B1. Fixes TASTART issue. First B2 (TIMERB and CREGB)
- v0.1.2 First production run for B3. (SDR and ICR)
- v0.2.0 First MINOR advance. B0+B1+B2+B3 tested and validated.
- v0.2.1 Fixes for Reload under Underflow issue.
- v0.2.2 First production run for B4 (TOD). It now passes test 01 and 02 in both NEW and OLD modes.
- B0. Some HCT parts are changed to HC
- B1. Split TIMER into modules for improved readability
- B2. Split TIMER into modules for improved readability
- B3. Issue #12. Fixed all issues for test 02
- B3. Master Switch for Mode Change. (Old vs NEW)
- B3. Some HC parts are changed to HCT
- B4. Added TOD PCB and SCH
- All boards. Published upgrade procedures
- All boards. Added pdfs for all schematic and pcbs for all versions for ease of access
- B1. Changes to Reload portion of TimerA pipeline to fix 01cmpold issue
- B2. Changes to Reload portion of TimerA pipeline to fix 01cmpold issue
- B3. Added switch to select OLD or NEW CIA
- All boards. Removed TARUNMODE from the ControlBus
- All boards. Updated for JLCPCB and PCBWAY capabilities
- All boards. Minor aesthetic changes to schematics
- All boards. Updated PDFs on the release
- B1. Optimized CNT edge detector
- B2. Optimized CNT edge detector
- B3. Fixed FLAG edge detector in ICR
- B3. Fixed SDR input and output issues from v0.1.2 (not sending nor receiving)
- B3. First release. SDR and ICR
- B2. Updates for JLCPCB capabilities
- All boards. Schematic review. Added /RES capacitor to prevent false restarts
- B2. First release.
- B1. Fixed additional cycle on forceload by removing second flipflop in the chain (rolled-back)
- B1. Added additionad dFF to Start before being fed into the timer
- B1. D and DZ moved to separate buses on schematic.
- B0. Routing optimized. D and DZ moved to separate buses on schematic. Silkscreen improved.
- B1 with TimerA and Control Register A. Ready for production.
- Mounting holes pads were covered with soldermask. Soldermask removed and pads properly labeled.
- Silkscreen fixes
- Updated gerber files
- B0 with DDRs, PORTs, and bus interface
- June 23, 2023. v0.2.2 released. Adds TOD (B4) and fixes more NEW to OLD issues. Now passes tests 01 and 02.
- March 26, 2023. v0.2.1 released. Fixes a missing IRQ issue on reload while underflowing. It also adds a selector for OLD vs NEW cia in ICR
- January 24, 2023. v0.2.0 released. Fixes a potential problem on B1 and B2 with CNT edge detector. It also fixes some bugs on B3. A cleanup of schematic, PCBs and PDFs for all boards has been done. TARUNMODE is removed from controlbus as it is not needed. This triggers a new MINOR version
- November 01, 2022. v0.1.2 released. Includes B3 (SDR+ICR) and some minor tweaks to all boards
- August 24, 2022. v0.1.1 released. Fixes a bug in B1 (TASTART) and adds B2. Minor routing fixes to all boards
- June 06, 2022. v0.1.0a released. It adds B1 to v0.1.0
- October 19, 2021. v0.1.0 is released. It add B0 to v0.1.0
- September 12th, 2021. Repository is now public. B0 schematic is 100% done. PCB layout is 100% done. It's currently being reviewed before sending it into production