This is a (very experimental) implementation of a MOS6526 using logisim. In order to use the simulation, Drass' Logisim implementation of a 6502 CPU has been used. (https://hackaday.io/project/174769-100mhz-ttl-6502)
Due to LOGISIM limitations, a "non-block" version (SBC6526_ex.circ) has been included. This is the latest version and the one that will be update from now on. The "block" version is somehow valid, but I offer no guarantee about its behaviour.
Please keep in mind, this is heavily untested, and it's only made public for reference, and for anyone who feels like taking a chance a the project to be able to try it. I can offer no guarantee on the behaviour of the simulation.
Feel free to reach me if there's anything I can for you.