SBC6526 is a single board computer built around A 65c02 CPU. It has been designed with a very specific purpose, that has defined both its name and its specs. I've been working for some time already on a MOS6526 (The famous CIA used in Commodore Computers) replica using 74xx logic series ICs. Testing was done on a real C64, but soon this prove to be a very limiting factor. So I begin working on a small SBC, designed entirely around the 6526, that should allow me to run as many tests, with no limitations at all.
The initial set of requisites was
- Continuosly variable clock, from 1MHz to as far as possible, in order to push my replica to its limits
- Clock Frequency Display. Useful, and should look very cool.
- No input at all. Program the ROM (more on this later) and just run a suite of tests for the 6526.
- Basic output.. Something like a 20x4 Character LCD will do.
- Easy, quick, and on board ROM programming. I will be modifiying the code continuosly, so this is very important.
- Include a 6522. Why not!? It can also be useful for the tests
- Include a socket for a 6526. Compatibility with old NMOS 6526 is not needed, although it would be nice.
- Allow testing of all 6526 pins. Ports, serial, /FLAG interrupt, etc
- Independent reset for 6526.
SBCv1 came to life, fulfilling this requirements. Howeever, after using it for some time, it show some weakness. SBCv1 has a 6522 and a 6526. A 4x40 LCD is used as display, driven by the 6526. This causes the display to blank when running some tests, and sometimes, crashed the LCD into an unrecoverable state, that requires a complete power down. This along some layout issues, forced the next revision.
0000 - 7FFF RAM 8000 - 87FF I/O BANK 0 - FREE 8800 - 8FFF I/O BANK 1 - CIA1 9000 - 97FF I/O BANK 2 - VIA 9800 - 9FFF I/O BANK 3 - CIAEXT A000 - A7FF I/O BANK 4 A800 - AFFF I/O BANK 5 B000 - B7FF I/O BANK 6 B800 - BFFF I/O BANK 7 C000 - FFFF RAM
Being my first attempt at creating a SBC, v1 had many flaws. There were some pull-up resistors missing, the PCB layout was a mess, the bootstrap code was... well... unreadable to be honest. Moreover, the CAD tool I choose for v1, Eagle Cad, has a nasty licensing which is pulling away many users. I decided to make the transition to KiCAD for the v2. It's still a work in progress, and completely untested, but feel free to take a look if you like.
SBCv2 adds a second 6526. There's a 40 pin DIP socket that accepts both a MOS6526 or any modern replacement. Second 6526 connects over a 40 pin IDC that matches the 74HCT6526 interface. The LCD is now driven by the 6522, so both 6526 are 100% usable for testing.
On SBCv1, TOD in the 6526 was used to determine clock speed. Now, a 60hz signal generated by the arduino goes into the 6522 for this purpose. SBC6526 can now startup and run with no 6526 connected at all.
The SBC6526 has no ROM. RAM exists between 0000-7FFF and C000-FFFF. As you know, the 6502 CPU needs the startup vectors to be present in the last segment of memory so, how does the SBC6526 boot?
An Arduino NANO handles the startup sequence. On startup, it brings BE low, disconnecting the 6502 from the address and data busses, and the R/W line. This also enables a pair of 8bit shift registers that handle from now on the address bus.
The RAM IC has 2 enable inputs. One is controled via the SBC Address Decoding logic, the other, directly by the ARDUINO. During BootStraping, RAMCE pulses with PHI2 (independent from the arduino) and the Arduino pulses CE line. This is a bit unorthodox and may cause some failures to write, if the arduino pulse happens when PHI2 is high. This is handled by trying several times to write.
When the ROM image is written, BE is released, and the 6502 is resetted by the Arduino itself.
Full schematic and PCB. The migration from EagleCAD to KiCAD has not been easy, as I was very much used to EagleCad. But the change as been worth the effort.
With little architectural changes from v1, original firmware will need just some minor changes. Most important one, LCD screen is now driven by the 6522 instead of the 6526. Also, the internal clock measurement has to be done also with the 6522. Memory map will be the same, with just a second CIA added into an empty IO Slot.
Java code to upload memory image to SBC
- Nothing
- Minor fixes to routing
- Right VCC hole was slightly offset. Fixed
- Removed /CE from arduino to RAM. As RAMCE pulses with PHI, it's not necessary, and we leave /CE tied to GND.
- Fixed RAM footprint, as it was too wide. Improved routing.
- Added current limiting resistor to LCD Contrast
- Bootstrap and Firmware published. Not completed, but working.
- Fixed a bug on LCD frequency meter footprint. Top row pads were reversed
- First draft of firmware, only for LOGISIM version
- Initial draft of bootstrap loader. Still not working.
- First v2 release
- First PCB run
- First and last v1 release
- It works, which is enough.