/
cgen.go
3555 lines (3174 loc) · 79.7 KB
/
cgen.go
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// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
package gc
import (
"cmd/internal/obj"
"cmd/internal/obj/ppc64"
"fmt"
)
// generate:
// res = n;
// simplifies and calls Thearch.Gmove.
// if wb is true, need to emit write barriers.
func Cgen(n, res *Node) {
cgen_wb(n, res, false)
}
func cgen_wb(n, res *Node, wb bool) {
if Debug['g'] != 0 {
op := "cgen"
if wb {
op = "cgen_wb"
}
Dump("\n"+op+"-n", n)
Dump(op+"-res", res)
}
if n == nil || n.Type == nil {
return
}
if res == nil || res.Type == nil {
Fatalf("cgen: res nil")
}
for n.Op == OCONVNOP {
n = n.Left
}
switch n.Op {
case OSLICE, OSLICEARR, OSLICESTR, OSLICE3, OSLICE3ARR:
cgen_slice(n, res, wb)
return
case OEFACE:
if res.Op != ONAME || !res.Addable || wb {
var n1 Node
Tempname(&n1, n.Type)
Cgen_eface(n, &n1)
cgen_wb(&n1, res, wb)
} else {
Cgen_eface(n, res)
}
return
case ODOTTYPE:
cgen_dottype(n, res, nil, wb)
return
case OAPPEND:
cgen_append(n, res)
return
}
if n.Ullman >= UINF {
if n.Op == OINDREG {
Fatalf("cgen: this is going to miscompile")
}
if res.Ullman >= UINF {
var n1 Node
Tempname(&n1, n.Type)
Cgen(n, &n1)
cgen_wb(&n1, res, wb)
return
}
}
if Isfat(n.Type) {
if n.Type.Width < 0 {
Fatalf("forgot to compute width for %v", n.Type)
}
sgen_wb(n, res, n.Type.Width, wb)
return
}
if !res.Addable {
if n.Ullman > res.Ullman {
if Ctxt.Arch.Regsize == 4 && Is64(n.Type) {
var n1 Node
Tempname(&n1, n.Type)
Cgen(n, &n1)
cgen_wb(&n1, res, wb)
return
}
var n1 Node
Regalloc(&n1, n.Type, res)
Cgen(n, &n1)
if n1.Ullman > res.Ullman {
Dump("n1", &n1)
Dump("res", res)
Fatalf("loop in cgen")
}
cgen_wb(&n1, res, wb)
Regfree(&n1)
return
}
var f int
if res.Ullman < UINF {
if Complexop(n, res) {
Complexgen(n, res)
return
}
f = 1 // gen thru register
switch n.Op {
case OLITERAL:
if Smallintconst(n) {
f = 0
}
case OREGISTER:
f = 0
}
if !Iscomplex[n.Type.Etype] && Ctxt.Arch.Regsize == 8 && !wb {
a := Thearch.Optoas(OAS, res.Type)
var addr obj.Addr
if Thearch.Sudoaddable(a, res, &addr) {
var p1 *obj.Prog
if f != 0 {
var n2 Node
Regalloc(&n2, res.Type, nil)
Cgen(n, &n2)
p1 = Thearch.Gins(a, &n2, nil)
Regfree(&n2)
} else {
p1 = Thearch.Gins(a, n, nil)
}
p1.To = addr
if Debug['g'] != 0 {
fmt.Printf("%v [ignore previous line]\n", p1)
}
Thearch.Sudoclean()
return
}
}
}
if Ctxt.Arch.Thechar == '8' {
// no registers to speak of
var n1, n2 Node
Tempname(&n1, n.Type)
Cgen(n, &n1)
Igen(res, &n2, nil)
cgen_wb(&n1, &n2, wb)
Regfree(&n2)
return
}
var n1 Node
Igen(res, &n1, nil)
cgen_wb(n, &n1, wb)
Regfree(&n1)
return
}
// update addressability for string, slice
// can't do in walk because n->left->addable
// changes if n->left is an escaping local variable.
switch n.Op {
case OSPTR, OLEN:
if Isslice(n.Left.Type) || Istype(n.Left.Type, TSTRING) {
n.Addable = n.Left.Addable
}
case OCAP:
if Isslice(n.Left.Type) {
n.Addable = n.Left.Addable
}
case OITAB:
n.Addable = n.Left.Addable
}
if wb {
if Simtype[res.Type.Etype] != Tptr {
Fatalf("cgen_wb of type %v", res.Type)
}
if n.Ullman >= UINF {
var n1 Node
Tempname(&n1, n.Type)
Cgen(n, &n1)
n = &n1
}
cgen_wbptr(n, res)
return
}
// Write barrier now handled. Code below this line can ignore wb.
if Ctxt.Arch.Thechar == '5' { // TODO(rsc): Maybe more often?
// if both are addressable, move
if n.Addable && res.Addable {
if Is64(n.Type) || Is64(res.Type) || n.Op == OREGISTER || res.Op == OREGISTER || Iscomplex[n.Type.Etype] || Iscomplex[res.Type.Etype] {
Thearch.Gmove(n, res)
} else {
var n1 Node
Regalloc(&n1, n.Type, nil)
Thearch.Gmove(n, &n1)
Cgen(&n1, res)
Regfree(&n1)
}
return
}
// if both are not addressable, use a temporary.
if !n.Addable && !res.Addable {
// could use regalloc here sometimes,
// but have to check for ullman >= UINF.
var n1 Node
Tempname(&n1, n.Type)
Cgen(n, &n1)
Cgen(&n1, res)
return
}
// if result is not addressable directly but n is,
// compute its address and then store via the address.
if !res.Addable {
var n1 Node
Igen(res, &n1, nil)
Cgen(n, &n1)
Regfree(&n1)
return
}
}
if Complexop(n, res) {
Complexgen(n, res)
return
}
if (Ctxt.Arch.Thechar == '6' || Ctxt.Arch.Thechar == '8') && n.Addable {
Thearch.Gmove(n, res)
return
}
if Ctxt.Arch.Thechar == '0' || Ctxt.Arch.Thechar == '7' || Ctxt.Arch.Thechar == '9' {
// if both are addressable, move
if n.Addable {
if n.Op == OREGISTER || res.Op == OREGISTER {
Thearch.Gmove(n, res)
} else {
var n1 Node
Regalloc(&n1, n.Type, nil)
Thearch.Gmove(n, &n1)
Cgen(&n1, res)
Regfree(&n1)
}
return
}
}
// if n is sudoaddable generate addr and move
if Ctxt.Arch.Thechar == '5' && !Is64(n.Type) && !Is64(res.Type) && !Iscomplex[n.Type.Etype] && !Iscomplex[res.Type.Etype] {
a := Thearch.Optoas(OAS, n.Type)
var addr obj.Addr
if Thearch.Sudoaddable(a, n, &addr) {
if res.Op != OREGISTER {
var n2 Node
Regalloc(&n2, res.Type, nil)
p1 := Thearch.Gins(a, nil, &n2)
p1.From = addr
if Debug['g'] != 0 {
fmt.Printf("%v [ignore previous line]\n", p1)
}
Thearch.Gmove(&n2, res)
Regfree(&n2)
} else {
p1 := Thearch.Gins(a, nil, res)
p1.From = addr
if Debug['g'] != 0 {
fmt.Printf("%v [ignore previous line]\n", p1)
}
}
Thearch.Sudoclean()
return
}
}
nl := n.Left
nr := n.Right
if nl != nil && nl.Ullman >= UINF {
if nr != nil && nr.Ullman >= UINF {
var n1 Node
Tempname(&n1, nl.Type)
Cgen(nl, &n1)
n2 := *n
n2.Left = &n1
Cgen(&n2, res)
return
}
}
// 64-bit ops are hard on 32-bit machine.
if Ctxt.Arch.Regsize == 4 && (Is64(n.Type) || Is64(res.Type) || n.Left != nil && Is64(n.Left.Type)) {
switch n.Op {
// math goes to cgen64.
case OMINUS,
OCOM,
OADD,
OSUB,
OMUL,
OLROT,
OLSH,
ORSH,
OAND,
OOR,
OXOR:
Thearch.Cgen64(n, res)
return
}
}
if Thearch.Cgen_float != nil && nl != nil && Isfloat[n.Type.Etype] && Isfloat[nl.Type.Etype] {
Thearch.Cgen_float(n, res)
return
}
if !Iscomplex[n.Type.Etype] && Ctxt.Arch.Regsize == 8 {
a := Thearch.Optoas(OAS, n.Type)
var addr obj.Addr
if Thearch.Sudoaddable(a, n, &addr) {
if res.Op == OREGISTER {
p1 := Thearch.Gins(a, nil, res)
p1.From = addr
} else {
var n2 Node
Regalloc(&n2, n.Type, nil)
p1 := Thearch.Gins(a, nil, &n2)
p1.From = addr
Thearch.Gins(a, &n2, res)
Regfree(&n2)
}
Thearch.Sudoclean()
return
}
}
var a int
switch n.Op {
default:
Dump("cgen", n)
Dump("cgen-res", res)
Fatalf("cgen: unknown op %v", Nconv(n, obj.FmtShort|obj.FmtSign))
case OOROR, OANDAND,
OEQ, ONE,
OLT, OLE,
OGE, OGT,
ONOT:
Bvgen(n, res, true)
return
case OPLUS:
Cgen(nl, res)
return
// unary
case OCOM:
a := Thearch.Optoas(OXOR, nl.Type)
var n1 Node
Regalloc(&n1, nl.Type, nil)
Cgen(nl, &n1)
var n2 Node
Nodconst(&n2, nl.Type, -1)
Thearch.Gins(a, &n2, &n1)
cgen_norm(n, &n1, res)
return
case OMINUS:
if Isfloat[nl.Type.Etype] {
nr = Nodintconst(-1)
Convlit(&nr, n.Type)
a = Thearch.Optoas(OMUL, nl.Type)
goto sbop
}
a := Thearch.Optoas(n.Op, nl.Type)
// unary
var n1 Node
Regalloc(&n1, nl.Type, res)
Cgen(nl, &n1)
if Ctxt.Arch.Thechar == '5' {
var n2 Node
Nodconst(&n2, nl.Type, 0)
Thearch.Gins(a, &n2, &n1)
} else if Ctxt.Arch.Thechar == '7' {
Thearch.Gins(a, &n1, &n1)
} else {
Thearch.Gins(a, nil, &n1)
}
cgen_norm(n, &n1, res)
return
case OSQRT:
var n1 Node
Regalloc(&n1, nl.Type, res)
Cgen(n.Left, &n1)
Thearch.Gins(Thearch.Optoas(OSQRT, nl.Type), &n1, &n1)
Thearch.Gmove(&n1, res)
Regfree(&n1)
return
case OGETG:
Thearch.Getg(res)
return
// symmetric binary
case OAND,
OOR,
OXOR,
OADD,
OMUL:
if n.Op == OMUL && Thearch.Cgen_bmul != nil && Thearch.Cgen_bmul(n.Op, nl, nr, res) {
break
}
a = Thearch.Optoas(n.Op, nl.Type)
goto sbop
// asymmetric binary
case OSUB:
a = Thearch.Optoas(n.Op, nl.Type)
goto abop
case OHMUL:
Thearch.Cgen_hmul(nl, nr, res)
case OCONV:
if Eqtype(n.Type, nl.Type) || Noconv(n.Type, nl.Type) {
Cgen(nl, res)
return
}
if Ctxt.Arch.Thechar == '8' {
var n1 Node
var n2 Node
Tempname(&n2, n.Type)
Mgen(nl, &n1, res)
Thearch.Gmove(&n1, &n2)
Thearch.Gmove(&n2, res)
Mfree(&n1)
break
}
var n1 Node
var n2 Node
if Ctxt.Arch.Thechar == '5' {
if nl.Addable && !Is64(nl.Type) {
Regalloc(&n1, nl.Type, res)
Thearch.Gmove(nl, &n1)
} else {
if n.Type.Width > int64(Widthptr) || Is64(nl.Type) || Isfloat[nl.Type.Etype] {
Tempname(&n1, nl.Type)
} else {
Regalloc(&n1, nl.Type, res)
}
Cgen(nl, &n1)
}
if n.Type.Width > int64(Widthptr) || Is64(n.Type) || Isfloat[n.Type.Etype] {
Tempname(&n2, n.Type)
} else {
Regalloc(&n2, n.Type, nil)
}
} else {
if n.Type.Width > nl.Type.Width {
// If loading from memory, do conversion during load,
// so as to avoid use of 8-bit register in, say, int(*byteptr).
switch nl.Op {
case ODOT, ODOTPTR, OINDEX, OIND, ONAME:
Igen(nl, &n1, res)
Regalloc(&n2, n.Type, res)
Thearch.Gmove(&n1, &n2)
Thearch.Gmove(&n2, res)
Regfree(&n2)
Regfree(&n1)
return
}
}
Regalloc(&n1, nl.Type, res)
Regalloc(&n2, n.Type, &n1)
Cgen(nl, &n1)
}
// if we do the conversion n1 -> n2 here
// reusing the register, then gmove won't
// have to allocate its own register.
Thearch.Gmove(&n1, &n2)
Thearch.Gmove(&n2, res)
if n2.Op == OREGISTER {
Regfree(&n2)
}
if n1.Op == OREGISTER {
Regfree(&n1)
}
case ODOT,
ODOTPTR,
OINDEX,
OIND,
ONAME: // PHEAP or PPARAMREF var
var n1 Node
Igen(n, &n1, res)
Thearch.Gmove(&n1, res)
Regfree(&n1)
// interface table is first word of interface value
case OITAB:
var n1 Node
Igen(nl, &n1, res)
n1.Type = n.Type
Thearch.Gmove(&n1, res)
Regfree(&n1)
case OSPTR:
// pointer is the first word of string or slice.
if Isconst(nl, CTSTR) {
var n1 Node
Regalloc(&n1, Types[Tptr], res)
p1 := Thearch.Gins(Thearch.Optoas(OAS, n1.Type), nil, &n1)
Datastring(nl.Val().U.(string), &p1.From)
p1.From.Type = obj.TYPE_ADDR
Thearch.Gmove(&n1, res)
Regfree(&n1)
break
}
var n1 Node
Igen(nl, &n1, res)
n1.Type = n.Type
Thearch.Gmove(&n1, res)
Regfree(&n1)
case OLEN:
if Istype(nl.Type, TMAP) || Istype(nl.Type, TCHAN) {
// map and chan have len in the first int-sized word.
// a zero pointer means zero length
var n1 Node
Regalloc(&n1, Types[Tptr], res)
Cgen(nl, &n1)
var n2 Node
Nodconst(&n2, Types[Tptr], 0)
p1 := Thearch.Ginscmp(OEQ, Types[Tptr], &n1, &n2, 0)
n2 = n1
n2.Op = OINDREG
n2.Type = Types[Simtype[TINT]]
Thearch.Gmove(&n2, &n1)
Patch(p1, Pc)
Thearch.Gmove(&n1, res)
Regfree(&n1)
break
}
if Istype(nl.Type, TSTRING) || Isslice(nl.Type) {
// both slice and string have len one pointer into the struct.
// a zero pointer means zero length
var n1 Node
Igen(nl, &n1, res)
n1.Type = Types[Simtype[TUINT]]
n1.Xoffset += int64(Array_nel)
Thearch.Gmove(&n1, res)
Regfree(&n1)
break
}
Fatalf("cgen: OLEN: unknown type %v", Tconv(nl.Type, obj.FmtLong))
case OCAP:
if Istype(nl.Type, TCHAN) {
// chan has cap in the second int-sized word.
// a zero pointer means zero length
var n1 Node
Regalloc(&n1, Types[Tptr], res)
Cgen(nl, &n1)
var n2 Node
Nodconst(&n2, Types[Tptr], 0)
p1 := Thearch.Ginscmp(OEQ, Types[Tptr], &n1, &n2, 0)
n2 = n1
n2.Op = OINDREG
n2.Xoffset = int64(Widthint)
n2.Type = Types[Simtype[TINT]]
Thearch.Gmove(&n2, &n1)
Patch(p1, Pc)
Thearch.Gmove(&n1, res)
Regfree(&n1)
break
}
if Isslice(nl.Type) {
var n1 Node
Igen(nl, &n1, res)
n1.Type = Types[Simtype[TUINT]]
n1.Xoffset += int64(Array_cap)
Thearch.Gmove(&n1, res)
Regfree(&n1)
break
}
Fatalf("cgen: OCAP: unknown type %v", Tconv(nl.Type, obj.FmtLong))
case OADDR:
if n.Bounded { // let race detector avoid nil checks
Disable_checknil++
}
Agen(nl, res)
if n.Bounded {
Disable_checknil--
}
case OCALLMETH:
cgen_callmeth(n, 0)
cgen_callret(n, res)
case OCALLINTER:
cgen_callinter(n, res, 0)
cgen_callret(n, res)
case OCALLFUNC:
cgen_call(n, 0)
cgen_callret(n, res)
case OMOD, ODIV:
if Isfloat[n.Type.Etype] || Thearch.Dodiv == nil {
a = Thearch.Optoas(n.Op, nl.Type)
goto abop
}
if nl.Ullman >= nr.Ullman {
var n1 Node
Regalloc(&n1, nl.Type, res)
Cgen(nl, &n1)
cgen_div(n.Op, &n1, nr, res)
Regfree(&n1)
} else {
var n2 Node
if !Smallintconst(nr) {
Regalloc(&n2, nr.Type, res)
Cgen(nr, &n2)
} else {
n2 = *nr
}
cgen_div(n.Op, nl, &n2, res)
if n2.Op != OLITERAL {
Regfree(&n2)
}
}
case OLSH, ORSH, OLROT:
Thearch.Cgen_shift(n.Op, n.Bounded, nl, nr, res)
}
return
// put simplest on right - we'll generate into left
// and then adjust it using the computation of right.
// constants and variables have the same ullman
// count, so look for constants specially.
//
// an integer constant we can use as an immediate
// is simpler than a variable - we can use the immediate
// in the adjustment instruction directly - so it goes
// on the right.
//
// other constants, like big integers or floating point
// constants, require a mov into a register, so those
// might as well go on the left, so we can reuse that
// register for the computation.
sbop: // symmetric binary
if nl.Ullman < nr.Ullman || (nl.Ullman == nr.Ullman && (Smallintconst(nl) || (nr.Op == OLITERAL && !Smallintconst(nr)))) {
nl, nr = nr, nl
}
abop: // asymmetric binary
var n1 Node
var n2 Node
if Ctxt.Arch.Thechar == '8' {
// no registers, sigh
if Smallintconst(nr) {
var n1 Node
Mgen(nl, &n1, res)
var n2 Node
Regalloc(&n2, nl.Type, &n1)
Thearch.Gmove(&n1, &n2)
Thearch.Gins(a, nr, &n2)
Thearch.Gmove(&n2, res)
Regfree(&n2)
Mfree(&n1)
} else if nl.Ullman >= nr.Ullman {
var nt Node
Tempname(&nt, nl.Type)
Cgen(nl, &nt)
var n2 Node
Mgen(nr, &n2, nil)
var n1 Node
Regalloc(&n1, nl.Type, res)
Thearch.Gmove(&nt, &n1)
Thearch.Gins(a, &n2, &n1)
Thearch.Gmove(&n1, res)
Regfree(&n1)
Mfree(&n2)
} else {
var n2 Node
Regalloc(&n2, nr.Type, res)
Cgen(nr, &n2)
var n1 Node
Regalloc(&n1, nl.Type, nil)
Cgen(nl, &n1)
Thearch.Gins(a, &n2, &n1)
Regfree(&n2)
Thearch.Gmove(&n1, res)
Regfree(&n1)
}
return
}
if nl.Ullman >= nr.Ullman {
Regalloc(&n1, nl.Type, res)
Cgen(nl, &n1)
if Smallintconst(nr) && Ctxt.Arch.Thechar != '0' && Ctxt.Arch.Thechar != '5' && Ctxt.Arch.Thechar != '7' && Ctxt.Arch.Thechar != '9' { // TODO(rsc): Check opcode for arm
n2 = *nr
} else {
Regalloc(&n2, nr.Type, nil)
Cgen(nr, &n2)
}
} else {
if Smallintconst(nr) && Ctxt.Arch.Thechar != '0' && Ctxt.Arch.Thechar != '5' && Ctxt.Arch.Thechar != '7' && Ctxt.Arch.Thechar != '9' { // TODO(rsc): Check opcode for arm
n2 = *nr
} else {
Regalloc(&n2, nr.Type, res)
Cgen(nr, &n2)
}
Regalloc(&n1, nl.Type, nil)
Cgen(nl, &n1)
}
Thearch.Gins(a, &n2, &n1)
if n2.Op != OLITERAL {
Regfree(&n2)
}
cgen_norm(n, &n1, res)
}
var sys_wbptr *Node
func cgen_wbptr(n, res *Node) {
if Curfn != nil {
if Curfn.Func.Nowritebarrier {
Yyerror("write barrier prohibited")
}
if Curfn.Func.WBLineno == 0 {
Curfn.Func.WBLineno = lineno
}
}
if Debug_wb > 0 {
Warn("write barrier")
}
var dst, src Node
Igen(res, &dst, nil)
if n.Op == OREGISTER {
src = *n
Regrealloc(&src)
} else {
Cgenr(n, &src, nil)
}
wbVar := syslook("writeBarrier", 0)
wbEnabled := Nod(ODOT, wbVar, newname(wbVar.Type.Type.Sym))
wbEnabled = typecheck(&wbEnabled, Erv)
pbr := Thearch.Ginscmp(ONE, Types[TUINT8], wbEnabled, Nodintconst(0), -1)
Thearch.Gins(Thearch.Optoas(OAS, Types[Tptr]), &src, &dst)
pjmp := Gbranch(obj.AJMP, nil, 0)
Patch(pbr, Pc)
var adst Node
Agenr(&dst, &adst, &dst)
p := Thearch.Gins(Thearch.Optoas(OAS, Types[Tptr]), &adst, nil)
a := &p.To
a.Type = obj.TYPE_MEM
a.Reg = int16(Thearch.REGSP)
a.Offset = Ctxt.FixedFrameSize()
p2 := Thearch.Gins(Thearch.Optoas(OAS, Types[Tptr]), &src, nil)
p2.To = p.To
p2.To.Offset += int64(Widthptr)
Regfree(&adst)
if sys_wbptr == nil {
sys_wbptr = writebarrierfn("writebarrierptr", Types[Tptr], Types[Tptr])
}
Ginscall(sys_wbptr, 0)
Patch(pjmp, Pc)
Regfree(&dst)
Regfree(&src)
}
func cgen_wbfat(n, res *Node) {
if Curfn != nil {
if Curfn.Func.Nowritebarrier {
Yyerror("write barrier prohibited")
}
if Curfn.Func.WBLineno == 0 {
Curfn.Func.WBLineno = lineno
}
}
if Debug_wb > 0 {
Warn("write barrier")
}
needType := true
funcName := "typedmemmove"
var dst, src Node
if n.Ullman >= res.Ullman {
Agenr(n, &src, nil)
Agenr(res, &dst, nil)
} else {
Agenr(res, &dst, nil)
Agenr(n, &src, nil)
}
p := Thearch.Gins(Thearch.Optoas(OAS, Types[Tptr]), &dst, nil)
a := &p.To
a.Type = obj.TYPE_MEM
a.Reg = int16(Thearch.REGSP)
a.Offset = Ctxt.FixedFrameSize()
if needType {
a.Offset += int64(Widthptr)
}
p2 := Thearch.Gins(Thearch.Optoas(OAS, Types[Tptr]), &src, nil)
p2.To = p.To
p2.To.Offset += int64(Widthptr)
Regfree(&dst)
if needType {
src.Type = Types[Tptr]
Thearch.Gins(Thearch.Optoas(OAS, Types[Tptr]), typename(n.Type), &src)
p3 := Thearch.Gins(Thearch.Optoas(OAS, Types[Tptr]), &src, nil)
p3.To = p2.To
p3.To.Offset -= 2 * int64(Widthptr)
}
Regfree(&src)
Ginscall(writebarrierfn(funcName, Types[Tptr], Types[Tptr]), 0)
}
// cgen_norm moves n1 to res, truncating to expected type if necessary.
// n1 is a register, and cgen_norm frees it.
func cgen_norm(n, n1, res *Node) {
switch Ctxt.Arch.Thechar {
case '6', '8':
// We use sized math, so the result is already truncated.
default:
switch n.Op {
case OADD, OSUB, OMUL, ODIV, OCOM, OMINUS:
// TODO(rsc): What about left shift?
Thearch.Gins(Thearch.Optoas(OAS, n.Type), n1, n1)
}
}
Thearch.Gmove(n1, res)
Regfree(n1)
}
func Mgen(n *Node, n1 *Node, rg *Node) {
n1.Op = OEMPTY
if n.Addable {
*n1 = *n
if n1.Op == OREGISTER || n1.Op == OINDREG {
reg[n.Reg-int16(Thearch.REGMIN)]++
}
return
}
Tempname(n1, n.Type)
Cgen(n, n1)
if n.Type.Width <= int64(Widthptr) || Isfloat[n.Type.Etype] {
n2 := *n1
Regalloc(n1, n.Type, rg)
Thearch.Gmove(&n2, n1)
}
}
func Mfree(n *Node) {
if n.Op == OREGISTER {
Regfree(n)
}
}
// allocate a register (reusing res if possible) and generate
// a = n
// The caller must call Regfree(a).
func Cgenr(n *Node, a *Node, res *Node) {
if Debug['g'] != 0 {
Dump("cgenr-n", n)
}
if Isfat(n.Type) {
Fatalf("cgenr on fat node")
}
if n.Addable {
Regalloc(a, n.Type, res)
Thearch.Gmove(n, a)
return
}
switch n.Op {
case ONAME,
ODOT,
ODOTPTR,
OINDEX,
OCALLFUNC,
OCALLMETH,
OCALLINTER:
var n1 Node
Igen(n, &n1, res)
Regalloc(a, Types[Tptr], &n1)
Thearch.Gmove(&n1, a)
Regfree(&n1)
default:
Regalloc(a, n.Type, res)
Cgen(n, a)
}
}
// allocate a register (reusing res if possible) and generate
// a = &n
// The caller must call Regfree(a).
// The generated code checks that the result is not nil.
func Agenr(n *Node, a *Node, res *Node) {
if Debug['g'] != 0 {
Dump("\nagenr-n", n)
}
nl := n.Left
nr := n.Right
switch n.Op {
case ODOT, ODOTPTR, OCALLFUNC, OCALLMETH, OCALLINTER:
var n1 Node
Igen(n, &n1, res)
Regalloc(a, Types[Tptr], &n1)
Agen(&n1, a)
Regfree(&n1)
case OIND:
Cgenr(n.Left, a, res)
Cgen_checknil(a)
case OINDEX:
if Ctxt.Arch.Thechar == '5' {
var p2 *obj.Prog // to be patched to panicindex.
w := uint32(n.Type.Width)
bounded := Debug['B'] != 0 || n.Bounded
var n1 Node
var n3 Node
if nr.Addable {
var tmp Node
if !Isconst(nr, CTINT) {
Tempname(&tmp, Types[TINT32])
}
if !Isconst(nl, CTSTR) {
Agenr(nl, &n3, res)
}
if !Isconst(nr, CTINT) {
p2 = Thearch.Cgenindex(nr, &tmp, bounded)
Regalloc(&n1, tmp.Type, nil)