making 17 entries in the PCCIF ringbuffer since memory is being refer…

…enced at index 16
docfate111 · Jan 7, 2024 · bc19ae6 · bc19ae6
1 parent 2e7fb85
commit bc19ae6
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Showing 2 changed files with 6 additions and 5 deletions.
diff --git a/firmwire/vendor/mtk/hw/PCCIFPeripheral.py b/firmwire/vendor/mtk/hw/PCCIFPeripheral.py
@@ -486,6 +486,7 @@ def hw_write(self, offset, size, value):
                 self.handle_SRAM_write()
             else:
                 if value >= len(self.ringbuffer.offsets):
+                    print(size, value, self.ringbuffer.offsets)
                     self.log.error(
                         f"PCCIF ring no too large (value: {value}, is only: {len(self.ringbuffer.offsets)})"
                     )

diff --git a/firmwire/vendor/mtk/soc/__init__.py b/firmwire/vendor/mtk/soc/__init__.py
@@ -102,12 +102,12 @@ class MT6765(MediaTekSOC):
     AFFINITY_ONLY_CPU_0 = b"\1"
     AFFINITY_ONLY_CPU_1 = b"\x02"
     PCCIF_VERSION = 1
-    SHM_QUEUE_NUM = 8
+    SHM_QUEUE_NUM = 17
     SHM_LAYOUT = {
-        "rx_sizes": [80, 80, 40, 80, 20, 20, 64, 0],
-        "tx_sizes": [128, 40, 8, 40, 20, 20, 64, 0],
-        "rx_sizes_exp": [12, 32, 8, 0, 0, 0, 8, 0],
-        "tx_sizes_exp": [12, 32, 8, 0, 0, 0, 8, 0],
+        "rx_sizes": [80, 80, 40, 80, 20, 20, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+        "tx_sizes": [128, 40, 8, 40, 20, 20, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+        "rx_sizes_exp": [12, 32, 8, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
+        "tx_sizes_exp": [12, 32, 8, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0],
     }
 
     name = "MT6765"