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Single Cycle & 5-stage Pipelined MIPS Simulator in Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 33 Commits
pipeline MIPS		pipeline MIPS
single cycle MIPS		single cycle MIPS
README.md		README.md

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Single Cycle / 5-stage Pipelined MIPS simulator

support 44 instructions


R-Type	ADD	ADDU	SUB	SUBU	AND	OR	XOR	NOR	SLLV	SRLV	SRAV	SRA	SLT	SLTU	NOOP
immediate	ADDI	ADDIU			ANDI	ORI	XORI		SLL	SRL			SLTI	SLTIU	LUI
Branch	BEQ	BGEZ	BGEZAL	BGTZ	BLEZ	BLTZ	BLTZAL	BNE
Jump	J	JAL	JR
Memory	LB	LBU	LH	LHU	LW	SB	SH	SW

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Single Cycle & 5-stage Pipelined MIPS Simulator in Verilog

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