docs/DSP: Fix SBCLR and SBSET being backwards

Dolphin has them with SBCLR as 1200 and SBSET as 1300 since the inital megacommit: https://github.com/dolphin-emu/dolphin/blob/775dc8a9c0c83f7a2f776e97f5b90385c759535a/Source/Plugins/Plugin_DSP_LLE/Src/opcodes.cpp#L67-L68
dolphin-emu · Aug 21, 2021 · 000f7b1 · 000f7b1
1 parent 13051ee
commit 000f7b1
Showing 1 changed file with 10 additions and 10 deletions.
diff --git a/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex b/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
@@ -2911,40 +2911,40 @@ \section{Alphabetical list of opcodes}
   \end{DSPOpcodeOperation}
 \end{DSPOpcode}
 
-\begin{DSPOpcode}{SBSET}
+\begin{DSPOpcode}{SBCLR}
   \begin{DSPOpcodeBytefield}{16}
     \monobitbox{4}{0001} & \monobitbox{4}{0010} & \monobitbox{4}{0000} & \monobitbox{4}{0iii}
   \end{DSPOpcodeBytefield}
 
   \begin{DSPOpcodeFormat}
-    SBSET #I
+    SBCLR #I
   \end{DSPOpcodeFormat}
 
   \begin{DSPOpcodeDescription}
-    \item Set bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be set with this instruction.
+    \item Clear bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be cleared with this instruction.
   \end{DSPOpcodeDescription}
 
   \begin{DSPOpcodeOperation}
-    $sr |= 1 << (I + 6)
+    $sr &= ~(1 << (I + 6))
     $pc++
   \end{DSPOpcodeOperation}
 \end{DSPOpcode}
 
-\begin{DSPOpcode}{SBCLR}
+\begin{DSPOpcode}{SBSET}
   \begin{DSPOpcodeBytefield}{16}
     \monobitbox{4}{0001} & \monobitbox{4}{0011} & \monobitbox{4}{0000} & \monobitbox{4}{0iii}
   \end{DSPOpcodeBytefield}
 
   \begin{DSPOpcodeFormat}
-    SBCLR #I
+    SBSET #I
   \end{DSPOpcodeFormat}
 
   \begin{DSPOpcodeDescription}
-    \item Clear bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be cleared with this instruction.
+    \item Set bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be set with this instruction.
   \end{DSPOpcodeDescription}
 
   \begin{DSPOpcodeOperation}
-    $sr &= ~(1 << (I + 6))
+    $sr |= 1 << (I + 6)
     $pc++
   \end{DSPOpcodeOperation}
 \end{DSPOpcode}
@@ -3649,8 +3649,8 @@ \section{Instructions sorted by opcode}
             &          &    &                                         \\
 LOOPI       &          & *  & 0001 0000 iiii iiii aaaa aaaa aaaa aaaa \\
 BLOOPI      &          & *  & 0001 0001 iiii iiii aaaa aaaa aaaa aaaa \\
-SBSET       &          & *  & 0001 0010 ???? ?iii                     \\
-SBCLR       &          & *  & 0001 0011 ???? ?iii                     \\
+SBCLR       &          & *  & 0001 0010 ???? ?iii                     \\
+SBSET       &          & *  & 0001 0011 ???? ?iii                     \\
 LSL/LSR     &          & *  & 0001 010r 0sss ssss                     \\
 ASL/ASR     &          & *  & 0001 010r 1sss ssss                     \\
 SI          &          & *  & 0001 0110 iiii iiii mmmm mmmm mmmm mmmm \\