Merge pull request #30 from Tilka/nits

Jit64IL: nits
dolphin-emu · Feb 4, 2014 · 158de30 · 158de30
2 parents 0c2a826 + 442796b
commit 158de30
Showing 1 changed file with 8 additions and 6 deletions.
diff --git a/Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp b/Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp
@@ -209,19 +209,21 @@ static OpArg regLocForInst(RegInfo& RI, InstLoc I) {
 		if (RI.regs[reg] == I)
 			return R(reg);
 
-	if (regGetSpill(RI, I) == 0)
+	unsigned slot = regGetSpill(RI, I);
+	if (!slot)
 		PanicAlert("Retrieving unknown spill slot?!");
-	return regLocForSlot(RI, regGetSpill(RI, I));
+	return regLocForSlot(RI, slot);
 }
 
 static OpArg fregLocForInst(RegInfo& RI, InstLoc I) {
 	for (auto& reg : FRegAllocOrder)
 		if (RI.fregs[reg] == I)
 			return R(reg);
 
-	if (fregGetSpill(RI, I) == 0)
+	unsigned slot = fregGetSpill(RI, I);
+	if (!slot)
 		PanicAlert("Retrieving unknown spill slot?!");
-	return fregLocForSlot(RI, fregGetSpill(RI, I));
+	return fregLocForSlot(RI, slot);
 }
 
 static void regClearInst(RegInfo& RI, InstLoc I) {
@@ -1344,9 +1346,9 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit) {
 		case FDNeg: {
 			if (!thisUsed) break;
 			X64Reg reg = fregURegWithMov(RI, I);
-			static const u64 GC_ALIGNED16(ssSignBits[2]) =
+			static const u64 GC_ALIGNED16(sdSignBits[2]) =
 				{0x8000000000000000ULL};
-			Jit->PXOR(reg, M((void*)&ssSignBits));
+			Jit->PXOR(reg, M((void*)&sdSignBits));
 			RI.fregs[reg] = I;
 			fregNormalRegClear(RI, I);
 			break;