[AArch64] Implement fcmp{u,o}

dolphin-emu · Jul 21, 2015 · 6a8b579 · 6a8b579
1 parent 3d6ee73
commit 6a8b579
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Showing 3 changed files with 92 additions and 2 deletions.
diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h
@@ -152,6 +152,7 @@ class JitArm64 : public JitBase, public Arm64Gen::ARM64CodeBlock
 	void fselx(UGeckoInstruction inst);
 	void fsubsx(UGeckoInstruction inst);
 	void fsubx(UGeckoInstruction inst);
+	void fcmpx(UGeckoInstruction inst);
 
 	// Paired
 	void ps_abs(UGeckoInstruction inst);

diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
@@ -392,3 +392,92 @@ void JitArm64::fsubx(UGeckoInstruction inst)
 
 	fpr.Unlock(V0);
 }
+
+void JitArm64::fcmpx(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(bJITFloatingPointOff);
+
+	u32 a = inst.FA, b = inst.FB;
+	int crf = inst.CRFD;
+
+	ARM64Reg VA = fpr.R(a);
+	ARM64Reg VB = fpr.R(b);
+
+	ARM64Reg WA = gpr.GetReg();
+	ARM64Reg XA = EncodeRegTo64(WA);
+
+	FixupBranch pNaN1, pNaN2, pNaN3, pLesser, pGreater;
+	FixupBranch continue1, continue2, continue3;
+	ORR(XA, ZR, 32, 0, true);
+
+	if (a != b)
+	{
+		m_float_emit.FCMP(EncodeRegToDouble(VA), EncodeRegToDouble(VA));
+
+		// if (B != B) or (A != A), goto NaN's jump target
+		pNaN1 = B(CC_NEQ);
+
+		m_float_emit.FCMP(EncodeRegToDouble(VB), EncodeRegToDouble(VB));
+
+		pNaN2 = B(CC_NEQ);
+	}
+
+	m_float_emit.FCMP(EncodeRegToDouble(VA), EncodeRegToDouble(VB));
+
+	if (a == b)
+		pNaN3 = B(CC_NEQ);
+
+	if (a != b)
+	{
+		// if B > A goto Greater's jump target
+		pGreater = B(CC_GT);
+	}
+
+	if (a != b)
+	{
+		// if B < A, goto Lesser's jump target
+		pLesser = B(CC_MI);
+	}
+
+	ORR(XA, XA, 64 - 63, 0, true);
+	continue1 = B();
+
+	if (a != b)
+	{
+		SetJumpTarget(pNaN1);
+		SetJumpTarget(pNaN2);
+	}
+	else
+	{
+		SetJumpTarget(pNaN3);
+	}
+
+	ORR(XA, XA, 64 - 61, 0, true);
+	ORR(XA, XA, 0, 0, true);
+
+	if (a != b)
+	{
+		continue2 = B();
+
+		SetJumpTarget(pGreater);
+		ORR(XA, XA, 0, 0, true);
+
+		continue3 = B();
+
+		SetJumpTarget(pLesser);
+		ORR(XA, XA, 64 - 62, 1, true);
+		ORR(XA, XA, 0, 0, true);
+	}
+
+	SetJumpTarget(continue1);
+	if (a != b)
+	{
+		SetJumpTarget(continue2);
+		SetJumpTarget(continue3);
+	}
+
+	STR(INDEX_UNSIGNED, XA, X29, PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
+
+	gpr.Unlock(WA);
+}
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
@@ -330,8 +330,8 @@ static GekkoOPTemplate table59[] =
 static GekkoOPTemplate table63[] =
 {
 	{264, &JitArm64::fabsx},                    // fabsx
-	{32,  &JitArm64::FallBackToInterpreter},    // fcmpo
-	{0,   &JitArm64::FallBackToInterpreter},    // fcmpu
+	{32,  &JitArm64::fcmpx},                    // fcmpo
+	{0,   &JitArm64::fcmpx},                    // fcmpu
 	{14,  &JitArm64::FallBackToInterpreter},    // fctiwx
 	{15,  &JitArm64::FallBackToInterpreter},    // fctiwzx
 	{72,  &JitArm64::fmrx},                     // fmrx