Fifo: Run/sync with the GPU on command processor register access

dolphin-emu · Jul 13, 2018 · 944c53d · 944c53d
1 parent 4826acd
commit 944c53d
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Showing 3 changed files with 39 additions and 14 deletions.
diff --git a/Source/Core/VideoCommon/CommandProcessor.cpp b/Source/Core/VideoCommon/CommandProcessor.cpp
@@ -216,6 +216,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
   }
 
   mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](u32) {
+                   Fifo::SyncGPUForRegisterAccess();
                    SetCpStatusRegister();
                    return m_CPStatusReg.Hex;
                  }),
@@ -252,18 +253,21 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
                      MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)),
                  MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance), 0xFFE0));
   mmio->Register(base | FIFO_RW_DISTANCE_HI,
-                 IsOnThread() ?
-                     MMIO::ComplexRead<u16>([](u32) {
-                       if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
-                         return ReadHigh(fifo.CPWritePointer - fifo.SafeCPReadPointer);
-                       else
-                         return ReadHigh(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
-                                         fifo.CPBase + 32);
-                     }) :
-                     MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadWriteDistance)),
+                 IsOnThread() ? MMIO::ComplexRead<u16>([](u32) {
+                   Fifo::SyncGPUForRegisterAccess();
+                   if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
+                     return ReadHigh(fifo.CPWritePointer - fifo.SafeCPReadPointer);
+                   else
+                     return ReadHigh(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
+                                     fifo.CPBase + 32);
+                 }) :
+                                MMIO::ComplexRead<u16>([](u32) {
+                                  Fifo::SyncGPUForRegisterAccess();
+                                  return ReadHigh(fifo.CPReadWriteDistance);
+                                }),
                  MMIO::ComplexWrite<u16>([](u32, u16 val) {
+                   Fifo::SyncGPUForRegisterAccess();
                    WriteHigh(fifo.CPReadWriteDistance, val);
-                   Fifo::SyncGPU(Fifo::SyncGPUReason::Other);
                    if (fifo.CPReadWriteDistance == 0)
                    {
                      GPFifo::ResetGatherPipe();
@@ -281,14 +285,23 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
                      MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
                  MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), 0xFFE0));
   mmio->Register(base | FIFO_READ_POINTER_HI,
-                 IsOnThread() ?
-                     MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.SafeCPReadPointer)) :
-                     MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer)),
+                 IsOnThread() ? MMIO::ComplexRead<u16>([](u32) {
+                   Fifo::SyncGPUForRegisterAccess();
+                   return ReadHigh(fifo.SafeCPReadPointer);
+                 }) :
+                                MMIO::ComplexRead<u16>([](u32) {
+                                  Fifo::SyncGPUForRegisterAccess();
+                                  return ReadHigh(fifo.CPReadPointer);
+                                }),
                  IsOnThread() ? MMIO::ComplexWrite<u16>([](u32, u16 val) {
+                   Fifo::SyncGPUForRegisterAccess();
                    WriteHigh(fifo.CPReadPointer, val);
                    fifo.SafeCPReadPointer = fifo.CPReadPointer;
                  }) :
-                                MMIO::DirectWrite<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer)));
+                                MMIO::ComplexWrite<u16>([](u32, u16 val) {
+                                  Fifo::SyncGPUForRegisterAccess();
+                                  WriteHigh(fifo.CPReadPointer, val);
+                                }));
 }
 
 void GatherPipeBursted()

diff --git a/Source/Core/VideoCommon/Fifo.cpp b/Source/Core/VideoCommon/Fifo.cpp
@@ -579,6 +579,14 @@ static void SyncGPUCallback(u64 ticks, s64 cyclesLate)
     CoreTiming::ScheduleEvent(next, s_event_sync_gpu, next);
 }
 
+void SyncGPUForRegisterAccess()
+{
+  if (!SConfig::GetInstance().bCPUThread || s_use_deterministic_gpu_thread)
+    RunGpuOnCpu(GPU_TIME_SLOT_SIZE);
+  else if (SConfig::GetInstance().bSyncGPU)
+    WaitForGpuThread(GPU_TIME_SLOT_SIZE);
+}
+
 // Initialize GPU - CPU thread syncing, this gives us a deterministic way to start the GPU thread.
 void Prepare()
 {

diff --git a/Source/Core/VideoCommon/Fifo.h b/Source/Core/VideoCommon/Fifo.h
@@ -33,6 +33,10 @@ enum class SyncGPUReason
 // In deterministic GPU thread mode this waits for the GPU to be done with pending work.
 void SyncGPU(SyncGPUReason reason, bool may_move_read_ptr = true);
 
+// In single core mode, this runs the GPU for a single slice.
+// In dual core mode, this synchronizes with the GPU thread.
+void SyncGPUForRegisterAccess();
+
 void PushFifoAuxBuffer(const void* ptr, size_t size);
 void* PopFifoAuxBuffer(size_t size);