[AArch64] Banish slowmem operations to farcode.

This improves performance pretty much across the board for games.
The increase in performance is mainly from removing some code from the main JIT blocks of code (pushing and popping millions of registers) and
throwing them in farcode where it doesn't pollute the icache.

Source/Core/Core/PowerPC/JitArm64/Jit.cpp

@@ -14,10 +14,13 @@
 
 using namespace Arm64Gen;
 
+static const int AARCH64_FARCODE_SIZE = 1024 * 1024 * 16;
+
 void JitArm64::Init()
 {
-	AllocCodeSpace(CODE_SIZE);
-	farcode.Init(SConfig::GetInstance().bMMU ? FARCODE_SIZE_MMU : FARCODE_SIZE);
+	size_t child_code_size = SConfig::GetInstance().bMMU ? FARCODE_SIZE_MMU : AARCH64_FARCODE_SIZE;
+	AllocCodeSpace(CODE_SIZE + child_code_size);
+	AddChildCodeSpace(&farcode, child_code_size);
 	jo.enableBlocklink = true;
 	jo.optimizeGatherPipe = true;
 	UpdateMemoryOptions();
@@ -36,16 +39,18 @@ void JitArm64::Init()
 
 void JitArm64::ClearCache()
 {
+	m_fault_to_handler.clear();
+	m_handler_to_loc.clear();
+
+	blocks.Clear();
 	ClearCodeSpace();
 	farcode.ClearCodeSpace();
-	blocks.Clear();
 	UpdateMemoryOptions();
 }
 
 void JitArm64::Shutdown()
 {
 	FreeCodeSpace();
-	farcode.Shutdown();
 	blocks.Shutdown();
 	asm_routines.Shutdown();
 }

Source/Core/Core/PowerPC/JitArm64/Jit.h

@@ -18,15 +18,6 @@
 
 #define PPCSTATE_OFF(elem) (offsetof(PowerPC::PowerPCState, elem))
 
-// A place to throw blocks of code we don't want polluting the cache, e.g. rarely taken
-// exception branches.
-class FarCodeCacheArm64 : public Arm64Gen::ARM64CodeBlock
-{
-public:
-	void Init(int size) { AllocCodeSpace(size); }
-	void Shutdown() { FreeCodeSpace(); }
-};
-
 // Some asserts to make sure we will be able to load everything
 static_assert(PPCSTATE_OFF(spr[1023]) <= 16380, "LDR(32bit) can't reach the last SPR");
 static_assert((PPCSTATE_OFF(ps[0][0]) % 8) == 0, "LDR(64bit VFP) requires FPRs to be 8 byte aligned");
@@ -184,6 +175,27 @@ class JitArm64 : public JitBase, public Arm64Gen::ARM64CodeBlock
 	void psq_st(UGeckoInstruction inst);
 
 private:
+
+	struct SlowmemHandler
+	{
+		ARM64Reg dest_reg;
+		ARM64Reg addr_reg;
+		BitSet32 gprs;
+		BitSet32 fprs;
+		u32 flags;
+		bool operator< (const SlowmemHandler& rhs) const
+		{
+			return !(dest_reg == rhs.dest_reg &&
+			       addr_reg == rhs.addr_reg &&
+				 gprs == rhs.gprs &&
+				 fprs == rhs.fprs &&
+				 flags == rhs.flags);
+		}
+	};
+
+	// <Fastmem fault location, slowmem handler location>
+	std::map<const u8*, std::pair<SlowmemHandler, const u8*>> m_fault_to_handler;
+	std::map<SlowmemHandler, const u8*> m_handler_to_loc;
 	Arm64GPRCache gpr;
 	Arm64FPRCache fpr;
 
@@ -194,7 +206,7 @@ class JitArm64 : public JitBase, public Arm64Gen::ARM64CodeBlock
 
 	ARM64FloatEmitter m_float_emit;
 
-	FarCodeCacheArm64 farcode;
+	Arm64Gen::ARM64CodeBlock farcode;
 	u8* nearcode; // Backed up when we switch to far code.
 
 	// Simple functions to switch between near and far code emitting
@@ -219,7 +231,9 @@ class JitArm64 : public JitBase, public Arm64Gen::ARM64CodeBlock
 	// Backpatching routines
 	bool DisasmLoadStore(const u8* ptr, u32* flags, Arm64Gen::ARM64Reg* reg);
 	void InitBackpatch();
-	u32 EmitBackpatchRoutine(ARM64XEmitter* emit, u32 flags, bool fastmem, bool do_padding, Arm64Gen::ARM64Reg RS, Arm64Gen::ARM64Reg addr);
+	u32 EmitBackpatchRoutine(u32 flags, bool fastmem, bool do_farcode,
+		Arm64Gen::ARM64Reg RS, Arm64Gen::ARM64Reg addr,
+		BitSet32 gprs_to_push = BitSet32(0), BitSet32 fprs_to_push = BitSet32(0));
 	// Loadstore routines
 	void SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 offset, bool update);
 	void SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s32 offset);