JitArm64: Increase farcode & nearcode cache size

[JosJuice]

This is a JitArm64 version of PR #12213.

Due to limitations on how far you can jump with a single AArch64 branch instruction, going above the former limit of 128 MiB of code (counting nearcode and farcode combined) requires a bit of restructuring. With the restructuring in place, the limit now is 256 MiB. See the new large comment in Jit.h for a description of the new memory layout.

[JosJuice]

@dreamsyntax Could you test Shadow the Hedgehog on AArch64 with this PR?

[dreamsyntax]

@dreamsyntax Could you test Shadow the Hedgehog on AArch64 with this PR?

Will do. If anyone else could please test other games/phones to see if the negative penalties such as longer stutter apply.

Time to first stutter & Jit Cache Clear in Logging:

Pixel 6
5.0-21336
36 minutes - this was surprising to me, as when we did the x86 changes it was previously within 5 minutes. Seems consistent now.

Relevant logs, happens at init on all branches but no detriment as below is not near/farcode clear.

07:53:144 Core/PowerPC/JitArm64/JitAsm.cpp:76 W[JIT]: Dispatcher is 0xd017591d7000
07:54:081 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:358 I[PowerPC]: Flush Instruction Cache! ICE=1
07:54:084 Common/ArmFPURoundMode.cpp:58 W[PowerPC]: Non-IEEE mode was requested, but host CPU is not known to support FEAT_AFP
07:54:099 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:468 I[PowerPC]: DBAT updated 536 80001fff 0
07:54:128 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:468 I[PowerPC]: DBAT updated 536 0 800001ff
07:54:153 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:491 I[PowerPC]: IBAT updated 528 80001fff 0
07:54:154 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:491 I[PowerPC]: IBAT updated 528 0 800001ff
07:54:155 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:468 I[PowerPC]: DBAT updated 541 0 1000002
07:54:182 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:468 I[PowerPC]: DBAT updated 540 0 810000ff
07:54:208 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:491 I[PowerPC]: IBAT updated 533 0 1000002
07:54:209 Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp:491 I[PowerPC]: IBAT updated 532 0 810000ff

(this PR)
No stutter in 2 hour test, same initial logs as above.

[dreamsyntax]

Completed tests on Android. Resolves Shadow stutter from JIT Cache clear

[JosJuice]

36 minutes - this was surprising to me, as when we did the x86 changes it was previously within 5 minutes. Seems consistent now.

If farcode was becoming full every five minutes, I think the reason for the improvement is PR #12319. But if it was nearcode becoming full, I'm less sure.

[dreamsyntax]

36 minutes - this was surprising to me, as when we did the x86 changes it was previously within 5 minutes. Seems consistent now.

If farcode was becoming full every five minutes, I think the reason for the improvement is PR #12319. But if it was nearcode becoming full, I'm less sure.

That checks out.

My prior ARM log was farcode, and it was before that PR.
#12213 (comment)

[AdmiralCurtiss]

This needs a rebase.

Should we merge this before the beta? It sounds like it works fine.

[JosJuice]

Sure, why not.