TLB cache fixes #1654
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TLB cache fixes #1654
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Added TLB state to the save state file.
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Fixes some MMU titles. |
| memset(ppcState.dtlb_pa, 0, sizeof(ppcState.dtlb_pa)); | ||
| ppcState.itlb_last = 0; | ||
| memset(ppcState.itlb_va, 0, sizeof(ppcState.itlb_va)); | ||
| memset(ppcState.itlb_pa, 0, sizeof(ppcState.itlb_pa)); | ||
| ppcState.pagetable_base = 0; |
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… always cleared on each invalidate command. Initialised the TLB cache to start from a consistent state on reset.
| UPTE2 PTE2; | ||
| PTE2.Hex = bswap((*(u32*)&pRAM[tlbe[0].pteg])); | ||
| if (PTE2.C == 0) | ||
| return 0; |
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Don't forget to update state version in State.cpp. |
| } | ||
| pteg_addr += 8; | ||
| if ((pteg_addr >> 28) == 1) |
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Updated PTE.R bit on Write and Instruction fetch. Added code to read the PTE from MEM2 if the PTE is stored there. Refactored the two hash functions to reduce code duplication. Updated save state version.
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Updated C bit on TLB cache hits.
Added TLB state to the save state file.
Removed the tag check in InvalidateTLBEntry. All four TLB entries are always cleared on each invalidate command.
Initialised the TLB cache to start from a consistent state on reset.
Stored a copy of the PTE in the TLB like the real hardware does.
Updated PTE.R bit on Write and Instruction fetch.
Added code to read the PTE from MEM2 if the PTE is stored there.
Refactored the two hash functions to reduce code duplication.
Updated save state version.