[AArch64] Optimize paired registers being used in double operations. #2911
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| // We are doing a full 128bit store because it takes 2 cycles on a Cortex-A57 to do a 128bit store. | ||
| // It would take longer to do an insert to a temporary and a 64bit store than to just do this. | ||
| ARM64Reg host_reg = reg.GetReg(); | ||
| m_float_emit->STR(128, INDEX_UNSIGNED, host_reg, X29, PPCSTATE_OFF(ps[preg][0])); |
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In particular this optimizes the case where a 32bit float is loaded via lfs, and then used in double operations. This happens very often in Gekko based code because the best way to load a 32bit value as a double is lfs since it automatically turns in to a double value. There are a few other implications of this in practice as well. Like if both of the paired registers are loaded via psq_l and then used in double operations it would be improved. Also if we implement a double register we've got to be careful to make sure we understand if it is in "lower" register or the full 128bit register.
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…tion [AArch64] Optimize paired registers being used in double operations.
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In particular this optimizes the case where a 32bit float is loaded via lfs, and then used in double operations.
This happens very often in Gekko based code because the best way to load a 32bit value as a double is lfs since it automatically turns in to a double value.
There are a few other implications of this in practice as well. Like if both of the paired registers are loaded via psq_l and then used in double
operations it would be improved.
Also if we implement a double register we've got to be careful to make sure we understand if it is in "lower" register or the full 128bit register.