JitCache: Support for VMEM + MSR bits #4095
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Specifically, don't make any assumptions about what effective addresses are used for code, and correctly handle changes to MSR.DR/MSR.IR. (Split off from dynamic-bat.)
Should be straightforward. Maybe useful for the purpose of testing.
This ID is reserved for invalid blocks. So this block can't be invalidated.
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Hi, this fix something for android? |
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@eddiebrook: No, it's not suposed to do so. |
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Oh i see, thanks for fast response. |
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Fixes the crashes in Harry Potter and Mario Tennis that were caused by the previous PR. |
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Oh, was that the bug? LGTM |
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Wanted to report that on my system (but also for other people too according to the forum), this commit causes a 5-6% speed slowdown. Tested on Win 10 - Intel e8600 - Geforce gtx950 |
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This is mostly a split of PR #1882 and a recreation of PR #4004. Only the last commit is touched at all.
This PR applies the JitCache changes required for dynamic bats:
It creates a second level cache based on the physical memory address to handle memory mirroring in an accurate way.
With this second level cache, we're able to use a bigger state as index. Here MSR.DR and MSR.IR are used. So address translation is known at compile time. This will be used later.
It also implements block unlinking. If a block is unlinked now, it is assured that we won't call this block any more. This is checked by INT3() within the jit64.
This change is