Release v0.3.0

[haixuanTao]

No description provided.

[phil-opp]

Thanks! Maybe we could reorder the changelog for v0.3 a bit to list the larger/breaking PRs first?

[haixuanTao]

Sure. I have replaced a fixed cache alignement with the constant aligned_vec cache alignment that is based on architecture.

// https://rust-lang.github.io/hashbrown/src/crossbeam_utils/cache_padded.rs.html#128-130
pub const CACHELINE_ALIGN: usize = {
    #[cfg(any(
        target_arch = "x86_64",
        target_arch = "aarch64",
        target_arch = "powerpc64",
    ))]
    {
        128
    }
    #[cfg(any(
        target_arch = "arm",
        target_arch = "mips",
        target_arch = "mips64",
        target_arch = "riscv64",
    ))]
    {
        32
    }
    #[cfg(target_arch = "s390x")]
    {
        256
    }
    #[cfg(not(any(
        target_arch = "x86_64",
        target_arch = "aarch64",
        target_arch = "powerpc64",
        target_arch = "arm",
        target_arch = "mips",
        target_arch = "mips64",
        target_arch = "riscv64",
        target_arch = "s390x",
    )))]
    {
        64
    }
};

Because, it was breaking the pip CI that is cross-compiling for x86. See: https://github.com/dora-rs/dora/actions/runs/6722305005/job/18269960724

Normally, this should be cross-architecture compatible as we are sending it as a slice.

[phil-opp]

The alignment is not about cache lines here, it's about the alignment required by arrow types. So instead of making it platform dependent, we should replace the avec macro invocation with the AVec::new constructor.

(I missed that avec creates cache-line aligned vectors. It just coincidentally matched the required alignment on the platform. I was building on.)

[haixuanTao]

Ok make sense. Thanks. Will do the change.