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codegenriscv64.cpp
8134 lines (7039 loc) · 289 KB
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codegenriscv64.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX RISCV64 Code Generator XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifdef TARGET_RISCV64
#include "emit.h"
#include "codegen.h"
#include "lower.h"
#include "gcinfo.h"
#include "gcinfoencoder.h"
bool CodeGen::genInstrWithConstant(instruction ins,
emitAttr attr,
regNumber reg1,
regNumber reg2,
ssize_t imm,
regNumber tmpReg,
bool inUnwindRegion /* = false */)
{
emitAttr size = EA_SIZE(attr);
// reg1 is usually a dest register
// reg2 is always source register
assert(tmpReg != reg2); // tmpReg can not match any source register
#ifdef DEBUG
switch (ins)
{
case INS_addi:
case INS_sb:
case INS_sh:
case INS_sw:
case INS_fsw:
case INS_sd:
case INS_fsd:
case INS_lb:
case INS_lh:
case INS_lw:
case INS_flw:
case INS_ld:
case INS_fld:
break;
default:
assert(!"Unexpected instruction in genInstrWithConstant");
break;
}
#endif
bool immFitsInIns = emitter::isValidSimm12(imm);
if (immFitsInIns)
{
// generate a single instruction that encodes the immediate directly
GetEmitter()->emitIns_R_R_I(ins, attr, reg1, reg2, imm);
}
else
{
// caller can specify REG_NA for tmpReg, when it "knows" that the immediate will always fit
assert(tmpReg != REG_NA);
// generate two or more instructions
// first we load the immediate into tmpReg
assert(!EA_IS_RELOC(size));
GetEmitter()->emitIns_I_la(size, tmpReg, imm);
regSet.verifyRegUsed(tmpReg);
// when we are in an unwind code region
// we record the extra instructions using unwindPadding()
if (inUnwindRegion)
{
compiler->unwindPadding();
}
if (ins == INS_addi)
{
GetEmitter()->emitIns_R_R_R(INS_add, attr, reg1, reg2, tmpReg);
}
else
{
GetEmitter()->emitIns_R_R_R(INS_add, attr, tmpReg, reg2, tmpReg);
GetEmitter()->emitIns_R_R_I(ins, attr, reg1, tmpReg, 0);
}
}
return immFitsInIns;
}
void CodeGen::genStackPointerAdjustment(ssize_t spDelta, regNumber tmpReg, bool* pTmpRegIsZero, bool reportUnwindData)
{
// Even though INS_addi is specified here, the encoder will choose either
// an INS_add_d or an INS_addi_d and encode the immediate as a positive value
//
bool wasTempRegisterUsedForImm =
!genInstrWithConstant(INS_addi, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, spDelta, tmpReg, true);
if (wasTempRegisterUsedForImm)
{
if (pTmpRegIsZero != nullptr)
{
*pTmpRegIsZero = false;
}
}
if (reportUnwindData)
{
// spDelta is negative in the prolog, positive in the epilog,
// but we always tell the unwind codes the positive value.
ssize_t spDeltaAbs = abs(spDelta);
unsigned unwindSpDelta = (unsigned)spDeltaAbs;
assert((ssize_t)unwindSpDelta == spDeltaAbs); // make sure that it fits in a unsigned
compiler->unwindAllocStack(unwindSpDelta);
}
}
void CodeGen::genPrologSaveRegPair(regNumber reg1,
regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
regNumber tmpReg,
bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta <= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
assert(genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2)); // registers must be both general-purpose, or both
// FP/SIMD
instruction ins = INS_sd;
if (genIsValidFloatReg(reg1))
{
ins = INS_fsd;
}
if (spDelta != 0)
{
// generate addi.d SP,SP,-imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
assert((spDelta + spOffset + 16) <= 0);
assert(spOffset <= 2031); // 2047-16
}
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg2, REG_SPBASE, spOffset + 8);
compiler->unwindSaveReg(reg2, spOffset + 8);
}
void CodeGen::genPrologSaveReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta <= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
instruction ins = INS_sd;
if (genIsValidFloatReg(reg1))
{
ins = INS_fsd;
}
if (spDelta != 0)
{
// generate daddiu SP,SP,-imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
}
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
}
void CodeGen::genEpilogRestoreRegPair(regNumber reg1,
regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
regNumber tmpReg,
bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta >= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
assert(genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2)); // registers must be both general-purpose, or both
// FP/SIMD
instruction ins = INS_ld;
if (genIsValidFloatReg(reg1))
{
ins = INS_fld;
}
if (spDelta != 0)
{
assert(!useSaveNextPair);
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg2, REG_SPBASE, spOffset + 8);
compiler->unwindSaveReg(reg2, spOffset + 8);
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
// generate daddiu SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
}
else
{
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg2, REG_SPBASE, spOffset + 8);
compiler->unwindSaveReg(reg2, spOffset + 8);
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
}
}
void CodeGen::genEpilogRestoreReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta >= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
instruction ins = INS_ld;
if (genIsValidFloatReg(reg1))
{
ins = INS_fld;
}
if (spDelta != 0)
{
// ld reg1, offset(SP)
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
// generate add SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
}
else
{
GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
}
}
// static
void CodeGen::genBuildRegPairsStack(regMaskTP regsMask, ArrayStack<RegPair>* regStack)
{
assert(regStack != nullptr);
assert(regStack->Height() == 0);
unsigned regsCount = genCountBits(regsMask);
while (regsMask != RBM_NONE)
{
regMaskTP reg1Mask = genFindLowestBit(regsMask);
regNumber reg1 = genRegNumFromMask(reg1Mask);
regsMask &= ~reg1Mask;
regsCount -= 1;
bool isPairSave = false;
if (regsCount > 0)
{
regMaskTP reg2Mask = genFindLowestBit(regsMask);
regNumber reg2 = genRegNumFromMask(reg2Mask);
if (reg2 == REG_NEXT(reg1))
{
// The JIT doesn't allow saving pair (S7,FP), even though the
// save_regp register pair unwind code specification allows it.
// The JIT always saves (FP,RA) as a pair, and uses the save_fpra
// unwind code. This only comes up in stress mode scenarios
// where callee-saved registers are not allocated completely
// from lowest-to-highest, without gaps.
if (reg1 != REG_FP)
{
// Both registers must have the same type to be saved as pair.
if (genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2))
{
isPairSave = true;
regsMask &= ~reg2Mask;
regsCount -= 1;
regStack->Push(RegPair(reg1, reg2));
}
}
}
}
if (!isPairSave)
{
regStack->Push(RegPair(reg1));
}
}
assert(regsCount == 0 && regsMask == RBM_NONE);
genSetUseSaveNextPairs(regStack);
}
// static
void CodeGen::genSetUseSaveNextPairs(ArrayStack<RegPair>* regStack)
{
for (int i = 1; i < regStack->Height(); ++i)
{
RegPair& curr = regStack->BottomRef(i);
RegPair prev = regStack->Bottom(i - 1);
if (prev.reg2 == REG_NA || curr.reg2 == REG_NA)
{
continue;
}
if (REG_NEXT(prev.reg2) != curr.reg1)
{
continue;
}
if (genIsValidFloatReg(prev.reg2) != genIsValidFloatReg(curr.reg1))
{
// It is possible to support changing of the last int pair with the first float pair,
// but it is very rare case and it would require superfluous changes in the unwinder.
continue;
}
curr.useSaveNextPair = true;
}
}
int CodeGen::genGetSlotSizeForRegsInMask(regMaskTP regsMask)
{
assert((regsMask & (RBM_CALLEE_SAVED | RBM_FP | RBM_RA)) == regsMask); // Do not expect anything else.
static_assert_no_msg(REGSIZE_BYTES == FPSAVE_REGSIZE_BYTES);
return REGSIZE_BYTES;
}
void CodeGen::genSaveCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset)
{
const int slotSize = genGetSlotSizeForRegsInMask(regsMask);
ArrayStack<RegPair> regStack(compiler->getAllocator(CMK_Codegen));
genBuildRegPairsStack(regsMask, ®Stack);
for (int i = 0; i < regStack.Height(); ++i)
{
RegPair regPair = regStack.Bottom(i);
if (regPair.reg2 != REG_NA)
{
// We can use two SD instructions.
genPrologSaveRegPair(regPair.reg1, regPair.reg2, spOffset, spDelta, regPair.useSaveNextPair, rsGetRsvdReg(),
nullptr);
spOffset += 2 * slotSize;
}
else
{
// No register pair; we use a SD instruction.
genPrologSaveReg(regPair.reg1, spOffset, spDelta, rsGetRsvdReg(), nullptr);
spOffset += slotSize;
}
spDelta = 0; // We've now changed SP already, if necessary; don't do it again.
}
}
void CodeGen::genSaveCalleeSavedRegistersHelp(regMaskTP regsToSaveMask, int lowestCalleeSavedOffset, int spDelta)
{
assert(spDelta <= 0);
unsigned regsToSaveCount = genCountBits(regsToSaveMask);
if (regsToSaveCount == 0)
{
if (spDelta != 0)
{
// Currently this is the case for varargs only
// whose size is MAX_REG_ARG * REGSIZE_BYTES = 64 bytes.
genStackPointerAdjustment(spDelta, rsGetRsvdReg(), nullptr, /* reportUnwindData */ true);
}
return;
}
assert((spDelta % 16) == 0);
assert(regsToSaveCount <= genCountBits(RBM_CALLEE_SAVED));
// Save integer registers at higher addresses than floating-point registers.
regMaskTP maskSaveRegsFloat = regsToSaveMask & RBM_ALLFLOAT;
regMaskTP maskSaveRegsInt = regsToSaveMask & ~maskSaveRegsFloat;
if (maskSaveRegsFloat != RBM_NONE)
{
genSaveCalleeSavedRegisterGroup(maskSaveRegsFloat, spDelta, lowestCalleeSavedOffset);
spDelta = 0;
lowestCalleeSavedOffset += genCountBits(maskSaveRegsFloat) * FPSAVE_REGSIZE_BYTES;
}
if (maskSaveRegsInt != RBM_NONE)
{
genSaveCalleeSavedRegisterGroup(maskSaveRegsInt, spDelta, lowestCalleeSavedOffset);
// No need to update spDelta, lowestCalleeSavedOffset since they're not used after this.
}
}
void CodeGen::genRestoreCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset)
{
const int slotSize = genGetSlotSizeForRegsInMask(regsMask);
ArrayStack<RegPair> regStack(compiler->getAllocator(CMK_Codegen));
genBuildRegPairsStack(regsMask, ®Stack);
int stackDelta = 0;
for (int i = 0; i < regStack.Height(); ++i)
{
bool lastRestoreInTheGroup = (i == regStack.Height() - 1);
bool updateStackDelta = lastRestoreInTheGroup && (spDelta != 0);
if (updateStackDelta)
{
// Update stack delta only if it is the last restore (the first save).
assert(stackDelta == 0);
stackDelta = spDelta;
}
RegPair regPair = regStack.Top(i);
if (regPair.reg2 != REG_NA)
{
spOffset -= 2 * slotSize;
genEpilogRestoreRegPair(regPair.reg1, regPair.reg2, spOffset, stackDelta, regPair.useSaveNextPair,
rsGetRsvdReg(), nullptr);
}
else
{
spOffset -= slotSize;
genEpilogRestoreReg(regPair.reg1, spOffset, stackDelta, rsGetRsvdReg(), nullptr);
}
}
}
void CodeGen::genRestoreCalleeSavedRegistersHelp(regMaskTP regsToRestoreMask, int lowestCalleeSavedOffset, int spDelta)
{
assert(spDelta >= 0);
unsigned regsToRestoreCount = genCountBits(regsToRestoreMask);
if (regsToRestoreCount == 0)
{
if (spDelta != 0)
{
// Currently this is the case for varargs only
// whose size is MAX_REG_ARG * REGSIZE_BYTES = 64 bytes.
genStackPointerAdjustment(spDelta, rsGetRsvdReg(), nullptr, /* reportUnwindData */ true);
}
return;
}
assert((spDelta % 16) == 0);
// We also can restore FP and RA, even though they are not in RBM_CALLEE_SAVED.
assert(regsToRestoreCount <= genCountBits(RBM_CALLEE_SAVED | RBM_FP | RBM_RA));
// Point past the end, to start. We predecrement to find the offset to load from.
static_assert_no_msg(REGSIZE_BYTES == FPSAVE_REGSIZE_BYTES);
int spOffset = lowestCalleeSavedOffset + regsToRestoreCount * REGSIZE_BYTES;
// Save integer registers at higher addresses than floating-point registers.
regMaskTP maskRestoreRegsFloat = regsToRestoreMask & RBM_ALLFLOAT;
regMaskTP maskRestoreRegsInt = regsToRestoreMask & ~maskRestoreRegsFloat;
// Restore in the opposite order of saving.
if (maskRestoreRegsInt != RBM_NONE)
{
int spIntDelta = (maskRestoreRegsFloat != RBM_NONE) ? 0 : spDelta; // should we delay the SP adjustment?
genRestoreCalleeSavedRegisterGroup(maskRestoreRegsInt, spIntDelta, spOffset);
spOffset -= genCountBits(maskRestoreRegsInt) * REGSIZE_BYTES;
}
if (maskRestoreRegsFloat != RBM_NONE)
{
// If there is any spDelta, it must be used here.
genRestoreCalleeSavedRegisterGroup(maskRestoreRegsFloat, spDelta, spOffset);
// No need to update spOffset since it's not used after this.
}
}
// clang-format on
void CodeGen::genFuncletProlog(BasicBlock* block)
{
#ifdef DEBUG
if (verbose)
printf("*************** In genFuncletProlog()\n");
#endif
assert(block != NULL);
assert(block->bbFlags & BBF_FUNCLET_BEG);
ScopedSetVariable<bool> _setGeneratingProlog(&compiler->compGeneratingProlog, true);
gcInfo.gcResetForBB();
compiler->unwindBegProlog();
regMaskTP maskSaveRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT;
regMaskTP maskSaveRegsInt = genFuncletInfo.fiSaveRegs & ~maskSaveRegsFloat;
// Funclets must always save RA and FP, since when we have funclets we must have an FP frame.
assert((maskSaveRegsInt & RBM_RA) != 0);
assert((maskSaveRegsInt & RBM_FP) != 0);
bool isFilter = (block->bbCatchTyp == BBCT_FILTER);
int frameSize = genFuncletInfo.fiSpDelta1;
regMaskTP maskArgRegsLiveIn;
if (isFilter)
{
maskArgRegsLiveIn = RBM_A0 | RBM_A1;
}
else if ((block->bbCatchTyp == BBCT_FINALLY) || (block->bbCatchTyp == BBCT_FAULT))
{
maskArgRegsLiveIn = RBM_NONE;
}
else
{
maskArgRegsLiveIn = RBM_A0;
}
#ifdef DEBUG
if (compiler->opts.disAsm)
{
printf("DEBUG: CodeGen::genFuncletProlog, frameType:%d\n\n", genFuncletInfo.fiFrameType);
}
#endif
int offset = 0;
if (genFuncletInfo.fiFrameType == 1)
{
// fiFrameType constraints:
assert(frameSize < 0);
assert(frameSize >= -2048);
assert(genFuncletInfo.fiSP_to_FPRA_save_delta < 2040);
genStackPointerAdjustment(frameSize, rsGetRsvdReg(), nullptr, /* reportUnwindData */ true);
GetEmitter()->emitIns_R_R_I(INS_sd, EA_PTRSIZE, REG_FP, REG_SPBASE, genFuncletInfo.fiSP_to_FPRA_save_delta);
compiler->unwindSaveReg(REG_FP, genFuncletInfo.fiSP_to_FPRA_save_delta);
GetEmitter()->emitIns_R_R_I(INS_sd, EA_PTRSIZE, REG_RA, REG_SPBASE, genFuncletInfo.fiSP_to_FPRA_save_delta + 8);
compiler->unwindSaveReg(REG_RA, genFuncletInfo.fiSP_to_FPRA_save_delta + 8);
maskSaveRegsInt &= ~(RBM_RA | RBM_FP); // We've saved these now
genSaveCalleeSavedRegistersHelp(maskSaveRegsInt | maskSaveRegsFloat, genFuncletInfo.fiSP_to_PSP_slot_delta + 8,
0);
}
else if (genFuncletInfo.fiFrameType == 2)
{
// fiFrameType constraints:
assert(frameSize < -2048);
offset = -frameSize - genFuncletInfo.fiSP_to_FPRA_save_delta;
int SP_delta = roundUp((UINT)offset, STACK_ALIGN);
offset = SP_delta - offset;
genStackPointerAdjustment(-SP_delta, rsGetRsvdReg(), nullptr, /* reportUnwindData */ true);
GetEmitter()->emitIns_R_R_I(INS_sd, EA_PTRSIZE, REG_FP, REG_SPBASE, offset);
compiler->unwindSaveReg(REG_FP, offset);
GetEmitter()->emitIns_R_R_I(INS_sd, EA_PTRSIZE, REG_RA, REG_SPBASE, offset + 8);
compiler->unwindSaveReg(REG_RA, offset + 8);
maskSaveRegsInt &= ~(RBM_RA | RBM_FP); // We've saved these now
offset = frameSize + SP_delta + genFuncletInfo.fiSP_to_PSP_slot_delta + 8;
genSaveCalleeSavedRegistersHelp(maskSaveRegsInt | maskSaveRegsFloat, offset, 0);
genStackPointerAdjustment(frameSize + SP_delta, rsGetRsvdReg(), nullptr,
/* reportUnwindData */ true);
}
else
{
unreached();
}
// This is the end of the OS-reported prolog for purposes of unwinding
compiler->unwindEndProlog();
// If there is no PSPSym (NativeAOT ABI), we are done. Otherwise, we need to set up the PSPSym in the functlet
// frame.
if (compiler->lvaPSPSym != BAD_VAR_NUM)
{
if (isFilter)
{
// This is the first block of a filter
// Note that register a1 = CallerSP of the containing function
// A1 is overwritten by the first Load (new callerSP)
// A2 is scratch when we have a large constant offset
// Load the CallerSP of the main function (stored in the PSP of the dynamically containing funclet or
// function)
genInstrWithConstant(INS_ld, EA_PTRSIZE, REG_A1, REG_A1, genFuncletInfo.fiCallerSP_to_PSP_slot_delta,
REG_A2, false);
regSet.verifyRegUsed(REG_A1);
// Store the PSP value (aka CallerSP)
genInstrWithConstant(INS_sd, EA_PTRSIZE, REG_A1, REG_SPBASE, genFuncletInfo.fiSP_to_PSP_slot_delta, REG_A2,
false);
// re-establish the frame pointer
genInstrWithConstant(INS_addi, EA_PTRSIZE, REG_FPBASE, REG_A1,
genFuncletInfo.fiFunction_CallerSP_to_FP_delta, REG_A2, false);
}
else // This is a non-filter funclet
{
// A3 is scratch, A2 can also become scratch.
// compute the CallerSP, given the frame pointer. a3 is scratch?
genInstrWithConstant(INS_addi, EA_PTRSIZE, REG_A3, REG_FPBASE,
-genFuncletInfo.fiFunction_CallerSP_to_FP_delta, REG_A2, false);
regSet.verifyRegUsed(REG_A3);
genInstrWithConstant(INS_sd, EA_PTRSIZE, REG_A3, REG_SPBASE, genFuncletInfo.fiSP_to_PSP_slot_delta, REG_A2,
false);
}
}
}
void CodeGen::genFuncletEpilog()
{
#ifdef DEBUG
if (verbose)
{
printf("*************** In genFuncletEpilog()\n");
}
#endif
ScopedSetVariable<bool> _setGeneratingEpilog(&compiler->compGeneratingEpilog, true);
bool unwindStarted = false;
int frameSize = genFuncletInfo.fiSpDelta1;
if (!unwindStarted)
{
// We can delay this until we know we'll generate an unwindable instruction, if necessary.
compiler->unwindBegEpilog();
unwindStarted = true;
}
regMaskTP maskRestoreRegsFloat = genFuncletInfo.fiSaveRegs & RBM_ALLFLOAT;
regMaskTP maskRestoreRegsInt = genFuncletInfo.fiSaveRegs & ~maskRestoreRegsFloat;
// Funclets must always save RA and FP, since when we have funclets we must have an FP frame.
assert((maskRestoreRegsInt & RBM_RA) != 0);
assert((maskRestoreRegsInt & RBM_FP) != 0);
#ifdef DEBUG
if (compiler->opts.disAsm)
{
printf("DEBUG: CodeGen::genFuncletEpilog, frameType:%d\n\n", genFuncletInfo.fiFrameType);
}
#endif
regMaskTP regsToRestoreMask = maskRestoreRegsInt | maskRestoreRegsFloat;
assert(frameSize < 0);
if (genFuncletInfo.fiFrameType == 1)
{
// fiFrameType constraints:
assert(frameSize >= -2048);
assert(genFuncletInfo.fiSP_to_FPRA_save_delta < 2040);
regsToRestoreMask &= ~(RBM_RA | RBM_FP); // We restore FP/RA at the end
genRestoreCalleeSavedRegistersHelp(regsToRestoreMask, genFuncletInfo.fiSP_to_PSP_slot_delta + 8, 0);
GetEmitter()->emitIns_R_R_I(INS_ld, EA_PTRSIZE, REG_RA, REG_SPBASE, genFuncletInfo.fiSP_to_FPRA_save_delta + 8);
compiler->unwindSaveReg(REG_RA, genFuncletInfo.fiSP_to_FPRA_save_delta + 8);
GetEmitter()->emitIns_R_R_I(INS_ld, EA_PTRSIZE, REG_FP, REG_SPBASE, genFuncletInfo.fiSP_to_FPRA_save_delta);
compiler->unwindSaveReg(REG_FP, genFuncletInfo.fiSP_to_FPRA_save_delta);
// generate daddiu SP,SP,imm
genStackPointerAdjustment(-frameSize, rsGetRsvdReg(), nullptr, /* reportUnwindData */ true);
}
else if (genFuncletInfo.fiFrameType == 2)
{
// fiFrameType constraints:
assert(frameSize < -2048);
int offset = -frameSize - genFuncletInfo.fiSP_to_FPRA_save_delta;
int SP_delta = roundUp((UINT)offset, STACK_ALIGN);
offset = SP_delta - offset;
// first, generate daddiu SP,SP,imm
genStackPointerAdjustment(-frameSize - SP_delta, rsGetRsvdReg(), nullptr,
/* reportUnwindData */ true);
int offset2 = frameSize + SP_delta + genFuncletInfo.fiSP_to_PSP_slot_delta + 8;
assert(offset2 < 2040); // can amend.
regsToRestoreMask &= ~(RBM_RA | RBM_FP); // We restore FP/RA at the end
genRestoreCalleeSavedRegistersHelp(regsToRestoreMask, offset2, 0);
GetEmitter()->emitIns_R_R_I(INS_ld, EA_PTRSIZE, REG_RA, REG_SPBASE, offset + 8);
compiler->unwindSaveReg(REG_RA, offset + 8);
GetEmitter()->emitIns_R_R_I(INS_ld, EA_PTRSIZE, REG_FP, REG_SPBASE, offset);
compiler->unwindSaveReg(REG_FP, offset);
// second, generate daddiu SP,SP,imm for remaine space.
genStackPointerAdjustment(SP_delta, rsGetRsvdReg(), nullptr, /* reportUnwindData */ true);
}
else
{
unreached();
}
GetEmitter()->emitIns_R_R_I(INS_jalr, emitActualTypeSize(TYP_I_IMPL), REG_R0, REG_RA, 0);
compiler->unwindReturn(REG_RA);
compiler->unwindEndEpilog();
}
void CodeGen::genCaptureFuncletPrologEpilogInfo()
{
if (!compiler->ehAnyFunclets())
{
return;
}
assert(isFramePointerUsed());
// The frame size and offsets must be finalized
assert(compiler->lvaDoneFrameLayout == Compiler::FINAL_FRAME_LAYOUT);
genFuncletInfo.fiFunction_CallerSP_to_FP_delta = genCallerSPtoFPdelta();
regMaskTP rsMaskSaveRegs = regSet.rsMaskCalleeSaved;
assert((rsMaskSaveRegs & RBM_RA) != 0);
assert((rsMaskSaveRegs & RBM_FP) != 0);
unsigned PSPSize = (compiler->lvaPSPSym != BAD_VAR_NUM) ? 8 : 0;
unsigned saveRegsCount = genCountBits(rsMaskSaveRegs);
assert((saveRegsCount == compiler->compCalleeRegsPushed) || (saveRegsCount == compiler->compCalleeRegsPushed - 1));
unsigned saveRegsPlusPSPSize =
roundUp((UINT)genTotalFrameSize(), STACK_ALIGN) - compiler->compLclFrameSize + PSPSize;
unsigned saveRegsPlusPSPSizeAligned = roundUp(saveRegsPlusPSPSize, STACK_ALIGN);
assert(compiler->lvaOutgoingArgSpaceSize % REGSIZE_BYTES == 0);
unsigned outgoingArgSpaceAligned = roundUp(compiler->lvaOutgoingArgSpaceSize, STACK_ALIGN);
unsigned maxFuncletFrameSizeAligned = saveRegsPlusPSPSizeAligned + outgoingArgSpaceAligned;
assert((maxFuncletFrameSizeAligned % STACK_ALIGN) == 0);
int SP_to_FPRA_save_delta = compiler->lvaOutgoingArgSpaceSize;
unsigned funcletFrameSize = saveRegsPlusPSPSize + compiler->lvaOutgoingArgSpaceSize;
unsigned funcletFrameSizeAligned = roundUp(funcletFrameSize, STACK_ALIGN);
assert(funcletFrameSizeAligned <= maxFuncletFrameSizeAligned);
unsigned funcletFrameAlignmentPad = funcletFrameSizeAligned - funcletFrameSize;
assert((funcletFrameAlignmentPad == 0) || (funcletFrameAlignmentPad == REGSIZE_BYTES));
if (maxFuncletFrameSizeAligned <= (2048 - 8))
{
genFuncletInfo.fiFrameType = 1;
saveRegsPlusPSPSize -= 2 * 8; // FP/RA
}
else
{
unsigned saveRegsPlusPSPAlignmentPad = saveRegsPlusPSPSizeAligned - saveRegsPlusPSPSize;
assert((saveRegsPlusPSPAlignmentPad == 0) || (saveRegsPlusPSPAlignmentPad == REGSIZE_BYTES));
genFuncletInfo.fiFrameType = 2;
saveRegsPlusPSPSize -= 2 * 8; // FP/RA
}
int CallerSP_to_PSP_slot_delta = -(int)saveRegsPlusPSPSize;
genFuncletInfo.fiSpDelta1 = -(int)funcletFrameSizeAligned;
int SP_to_PSP_slot_delta = funcletFrameSizeAligned - saveRegsPlusPSPSize;
/* Now save it for future use */
genFuncletInfo.fiSaveRegs = rsMaskSaveRegs;
genFuncletInfo.fiSP_to_FPRA_save_delta = SP_to_FPRA_save_delta;
genFuncletInfo.fiSP_to_PSP_slot_delta = SP_to_PSP_slot_delta;
genFuncletInfo.fiCallerSP_to_PSP_slot_delta = CallerSP_to_PSP_slot_delta;
#ifdef DEBUG
if (verbose)
{
printf("\n");
printf("Funclet prolog / epilog info\n");
printf(" Save regs: ");
dspRegMask(genFuncletInfo.fiSaveRegs);
printf("\n");
printf(" Function CallerSP-to-FP delta: %d\n", genFuncletInfo.fiFunction_CallerSP_to_FP_delta);
printf(" SP to FP/RA save location delta: %d\n", genFuncletInfo.fiSP_to_FPRA_save_delta);
printf(" Frame type: %d\n", genFuncletInfo.fiFrameType);
printf(" SP delta 1: %d\n", genFuncletInfo.fiSpDelta1);
if (compiler->lvaPSPSym != BAD_VAR_NUM)
{
if (CallerSP_to_PSP_slot_delta !=
compiler->lvaGetCallerSPRelativeOffset(compiler->lvaPSPSym)) // for debugging
{
printf("lvaGetCallerSPRelativeOffset(lvaPSPSym): %d\n",
compiler->lvaGetCallerSPRelativeOffset(compiler->lvaPSPSym));
}
}
}
assert(genFuncletInfo.fiSP_to_FPRA_save_delta >= 0);
#endif // DEBUG
}
void CodeGen::genFnEpilog(BasicBlock* block)
{
#ifdef DEBUG
if (verbose)
{
printf("*************** In genFnEpilog()\n");
}
#endif // DEBUG
ScopedSetVariable<bool> _setGeneratingEpilog(&compiler->compGeneratingEpilog, true);
VarSetOps::Assign(compiler, gcInfo.gcVarPtrSetCur, GetEmitter()->emitInitGCrefVars);
gcInfo.gcRegGCrefSetCur = GetEmitter()->emitInitGCrefRegs;
gcInfo.gcRegByrefSetCur = GetEmitter()->emitInitByrefRegs;
#ifdef DEBUG
if (compiler->opts.dspCode)
{
printf("\n__epilog:\n");
}
if (verbose)
{
printf("gcVarPtrSetCur=%s ", VarSetOps::ToString(compiler, gcInfo.gcVarPtrSetCur));
dumpConvertedVarSet(compiler, gcInfo.gcVarPtrSetCur);
printf(", gcRegGCrefSetCur=");
printRegMaskInt(gcInfo.gcRegGCrefSetCur);
GetEmitter()->emitDispRegSet(gcInfo.gcRegGCrefSetCur);
printf(", gcRegByrefSetCur=");
printRegMaskInt(gcInfo.gcRegByrefSetCur);
GetEmitter()->emitDispRegSet(gcInfo.gcRegByrefSetCur);
printf("\n");
}
#endif // DEBUG
bool jmpEpilog = ((block->bbFlags & BBF_HAS_JMP) != 0);
GenTree* lastNode = block->lastNode();
// Method handle and address info used in case of jump epilog
CORINFO_METHOD_HANDLE methHnd = nullptr;
CORINFO_CONST_LOOKUP addrInfo;
addrInfo.addr = nullptr;
addrInfo.accessType = IAT_VALUE;
if (jmpEpilog && (lastNode->gtOper == GT_JMP))
{
methHnd = (CORINFO_METHOD_HANDLE)lastNode->AsVal()->gtVal1;
compiler->info.compCompHnd->getFunctionEntryPoint(methHnd, &addrInfo);
}
compiler->unwindBegEpilog();
if (jmpEpilog)
{
SetHasTailCalls(true);
noway_assert(block->bbJumpKind == BBJ_RETURN);
noway_assert(block->GetFirstLIRNode() != nullptr);
/* figure out what jump we have */
GenTree* jmpNode = lastNode;
#if !FEATURE_FASTTAILCALL
noway_assert(jmpNode->gtOper == GT_JMP);
#else // FEATURE_FASTTAILCALL
// armarch
// If jmpNode is GT_JMP then gtNext must be null.
// If jmpNode is a fast tail call, gtNext need not be null since it could have embedded stmts.
noway_assert((jmpNode->gtOper != GT_JMP) || (jmpNode->gtNext == nullptr));
// Could either be a "jmp method" or "fast tail call" implemented as epilog+jmp
noway_assert((jmpNode->gtOper == GT_JMP) ||
((jmpNode->gtOper == GT_CALL) && jmpNode->AsCall()->IsFastTailCall()));
// The next block is associated with this "if" stmt
if (jmpNode->gtOper == GT_JMP)
#endif // FEATURE_FASTTAILCALL
{
// Simply emit a jump to the methodHnd. This is similar to a call so we can use
// the same descriptor with some minor adjustments.
assert(methHnd != nullptr);
assert(addrInfo.addr != nullptr);
emitter::EmitCallType callType;
void* addr;
regNumber indCallReg;
switch (addrInfo.accessType)
{
case IAT_VALUE:
// TODO-RISCV64-CQ: using B/BL for optimization.
case IAT_PVALUE:
// Load the address into a register, load indirect and call through a register
// We have to use REG_INDIRECT_CALL_TARGET_REG since we assume the argument registers are in use
callType = emitter::EC_INDIR_R;
indCallReg = REG_INDIRECT_CALL_TARGET_REG;
addr = NULL;
instGen_Set_Reg_To_Imm(EA_HANDLE_CNS_RELOC, indCallReg, (ssize_t)addrInfo.addr);
if (addrInfo.accessType == IAT_PVALUE)
{
GetEmitter()->emitIns_R_R_I(INS_ld, EA_PTRSIZE, indCallReg, indCallReg, 0);
regSet.verifyRegUsed(indCallReg);
}
break;
case IAT_RELPVALUE:
{
// Load the address into a register, load relative indirect and call through a register
// We have to use R12 since we assume the argument registers are in use
// LR is used as helper register right before it is restored from stack, thus,
// all relative address calculations are performed before LR is restored.
callType = emitter::EC_INDIR_R;
indCallReg = REG_T2;
addr = NULL;
regSet.verifyRegUsed(indCallReg);
break;
}
case IAT_PPVALUE:
default:
NO_WAY("Unsupported JMP indirection");
}
/* Simply emit a jump to the methodHnd. This is similar to a call so we can use
* the same descriptor with some minor adjustments.
*/
genPopCalleeSavedRegisters(true);
// clang-format off
GetEmitter()->emitIns_Call(callType,
methHnd,
INDEBUG_LDISASM_COMMA(nullptr)
addr,
0, // argSize
EA_UNKNOWN // retSize
MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(EA_UNKNOWN), // secondRetSize
gcInfo.gcVarPtrSetCur,
gcInfo.gcRegGCrefSetCur,
gcInfo.gcRegByrefSetCur,
DebugInfo(),
indCallReg, // ireg
REG_NA, // xreg
0, // xmul
0, // disp
true); // isJump
// clang-format on
CLANG_FORMAT_COMMENT_ANCHOR;
}
#if FEATURE_FASTTAILCALL
else
{
genPopCalleeSavedRegisters(true);
genCallInstruction(jmpNode->AsCall());
}
#endif // FEATURE_FASTTAILCALL
}
else
{
genPopCalleeSavedRegisters(false);
GetEmitter()->emitIns_R_R_I(INS_jalr, EA_PTRSIZE, REG_R0, REG_RA, 0);
compiler->unwindReturn(REG_RA);
}
compiler->unwindEndEpilog();
}
void CodeGen::genSetPSPSym(regNumber initReg, bool* pInitRegZeroed)