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emit.h
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emit.h
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*****************************************************************************/
#ifndef _EMIT_H_
#define _EMIT_H_
#include "instr.h"
#ifndef _GCINFO_H_
#include "gcinfo.h"
#endif
#include "jitgcinfo.h"
/*****************************************************************************/
#ifdef _MSC_VER
#pragma warning(disable : 4200) // allow arrays of 0 size inside structs
#endif
/*****************************************************************************/
#if 0
#define EMITVERBOSE 1
#else
#define EMITVERBOSE (emitComp->verbose)
#endif
#if 0
#define EMIT_GC_VERBOSE 0
#else
#define EMIT_GC_VERBOSE (emitComp->verbose)
#endif
#if 1
#define EMIT_INSTLIST_VERBOSE 0
#else
#define EMIT_INSTLIST_VERBOSE (emitComp->verbose)
#endif
#ifdef TARGET_XARCH
#define EMIT_BACKWARDS_NAVIGATION 1 // If 1, enable backwards navigation code for MIR (insGroup/instrDesc).
#else
#define EMIT_BACKWARDS_NAVIGATION 0
#endif
/*****************************************************************************/
#ifdef DEBUG
#define DEBUG_EMIT 1
#else
#define DEBUG_EMIT 0
#endif
#if EMITTER_STATS
void emitterStats(FILE* fout);
void emitterStaticStats(FILE* fout); // Static stats about the emitter (data structure offsets, sizes, etc.)
#endif
void printRegMaskInt(regMaskTP mask);
/*****************************************************************************/
/* Forward declarations */
class emitLocation;
class emitter;
struct insGroup;
typedef void (*emitSplitCallbackType)(void* context, emitLocation* emitLoc);
/*****************************************************************************/
//-----------------------------------------------------------------------------
inline bool needsGC(GCtype gcType)
{
if (gcType == GCT_NONE)
{
return false;
}
else
{
assert(gcType == GCT_GCREF || gcType == GCT_BYREF);
return true;
}
}
//-----------------------------------------------------------------------------
#ifdef DEBUG
inline bool IsValidGCtype(GCtype gcType)
{
return (gcType == GCT_NONE || gcType == GCT_GCREF || gcType == GCT_BYREF);
}
// Get a string name to represent the GC type
inline const char* GCtypeStr(GCtype gcType)
{
switch (gcType)
{
case GCT_NONE:
return "npt";
case GCT_GCREF:
return "gcr";
case GCT_BYREF:
return "byr";
default:
assert(!"Invalid GCtype");
return "err";
}
}
#endif // DEBUG
/*****************************************************************************/
#if DEBUG_EMIT
#define INTERESTING_JUMP_NUM -1 // set to 0 to see all jump info
//#define INTERESTING_JUMP_NUM 0
#endif
/*****************************************************************************
*
* Represent an emitter location.
*/
class emitLocation
{
public:
emitLocation() : ig(nullptr), codePos(0)
{
}
emitLocation(insGroup* _ig) : ig(_ig), codePos(0)
{
}
emitLocation(insGroup* _ig, unsigned _codePos)
{
SetLocation(_ig, _codePos);
}
emitLocation(emitter* emit)
{
CaptureLocation(emit);
}
emitLocation(void* emitCookie) : ig((insGroup*)emitCookie), codePos(0)
{
}
// A constructor for code that needs to call it explicitly.
void Init()
{
*this = emitLocation();
}
void CaptureLocation(emitter* emit);
void SetLocation(insGroup* _ig, unsigned _codePos);
void SetLocation(emitLocation newLocation);
bool IsCurrentLocation(emitter* emit) const;
// This function is highly suspect, since it presumes knowledge of the codePos "cookie",
// and doesn't look at the 'ig' pointer.
bool IsOffsetZero() const
{
return (codePos == 0);
}
UNATIVE_OFFSET CodeOffset(emitter* emit) const;
insGroup* GetIG() const
{
return ig;
}
int GetInsNum() const;
int GetInsOffset() const;
bool operator!=(const emitLocation& other) const
{
return (ig != other.ig) || (codePos != other.codePos);
}
bool operator==(const emitLocation& other) const
{
return !(*this != other);
}
bool Valid() const
{
// Things we could validate:
// 1. the instruction group pointer is non-nullptr.
// 2. 'ig' is a legal pointer to an instruction group.
// 3. 'codePos' is a legal offset into 'ig'.
// Currently, we just do #1.
// #2 and #3 should only be done in DEBUG, if they are implemented.
if (ig == nullptr)
{
return false;
}
return true;
}
UNATIVE_OFFSET GetFuncletPrologOffset(emitter* emit) const;
bool IsPreviousInsNum(emitter* emit) const;
#ifdef DEBUG
void Print(LONG compMethodID) const;
#endif // DEBUG
private:
insGroup* ig; // the instruction group
unsigned codePos; // the code position within the IG (see emitCurOffset())
};
/************************************************************************/
/* The following describes an instruction group */
/************************************************************************/
enum insGroupPlaceholderType : unsigned char
{
IGPT_PROLOG, // currently unused
IGPT_EPILOG,
#if defined(FEATURE_EH_FUNCLETS)
IGPT_FUNCLET_PROLOG,
IGPT_FUNCLET_EPILOG,
#endif // FEATURE_EH_FUNCLETS
};
#if defined(_MSC_VER) && defined(TARGET_ARM)
// ARM aligns structures that contain 64-bit ints or doubles on 64-bit boundaries. This causes unwanted
// padding to be added to the end, so sizeof() is unnecessarily big.
#pragma pack(push)
#pragma pack(4)
#endif // defined(_MSC_VER) && defined(TARGET_ARM)
struct insPlaceholderGroupData
{
insGroup* igPhNext;
BasicBlock* igPhBB;
VARSET_TP igPhInitGCrefVars;
regMaskTP igPhInitGCrefRegs;
regMaskTP igPhInitByrefRegs;
VARSET_TP igPhPrevGCrefVars;
regMaskTP igPhPrevGCrefRegs;
regMaskTP igPhPrevByrefRegs;
insGroupPlaceholderType igPhType;
}; // end of struct insPlaceholderGroupData
struct insGroup
{
insGroup* igNext;
#if EMIT_BACKWARDS_NAVIGATION
insGroup* igPrev;
#endif
#ifdef DEBUG
insGroup* igSelf; // for consistency checking
#endif
#if defined(DEBUG) || defined(LATE_DISASM)
weight_t igWeight; // the block weight used for this insGroup
double igPerfScore; // The PerfScore for this insGroup
#endif
#ifdef DEBUG
BasicBlock* lastGeneratedBlock; // The last block that generated code into this insGroup.
jitstd::list<BasicBlock*> igBlocks; // All the blocks that generated code into this insGroup.
size_t igDataSize; // size of instrDesc data pointed to by 'igData'
#endif
UNATIVE_OFFSET igNum; // for ordering (and display) purposes
UNATIVE_OFFSET igOffs; // offset of this group within method
unsigned int igFuncIdx; // Which function/funclet does this belong to? (Index into Compiler::compFuncInfos array.)
unsigned short igFlags; // see IGF_xxx below
unsigned short igSize; // # of bytes of code in this group
#if FEATURE_LOOP_ALIGN
insGroup* igLoopBackEdge; // "last" back-edge that branches back to an aligned loop head.
#endif
#define IGF_GC_VARS 0x0001 // new set of live GC ref variables
#define IGF_BYREF_REGS 0x0002 // new set of live by-ref registers
#if defined(FEATURE_EH_FUNCLETS) && defined(TARGET_ARM)
#define IGF_FINALLY_TARGET 0x0004 // this group is the start of a basic block that is returned to after a finally.
#endif // defined(FEATURE_EH_FUNCLETS) && defined(TARGET_ARM)
#define IGF_FUNCLET_PROLOG 0x0008 // this group belongs to a funclet prolog
#define IGF_FUNCLET_EPILOG 0x0010 // this group belongs to a funclet epilog.
#define IGF_EPILOG 0x0020 // this group belongs to a main function epilog
#define IGF_NOGCINTERRUPT 0x0040 // this IG is in a no-interrupt region (prolog, epilog, etc.)
#define IGF_UPD_ISZ 0x0080 // some instruction sizes updated
#define IGF_PLACEHOLDER 0x0100 // this is a placeholder group, to be filled in later
#define IGF_EXTEND 0x0200 // this block is conceptually an extension of the previous block
// and the emitter should continue to track GC info as if there was no new block.
#define IGF_HAS_ALIGN 0x0400 // this group contains an alignment instruction(s) at the end to align either the next
// IG, or, if this IG contains with an unconditional branch, some subsequent IG.
#define IGF_REMOVED_ALIGN 0x0800 // IG was marked as having an alignment instruction(s), but was later unmarked
// without updating the IG's size/offsets.
#define IGF_HAS_REMOVABLE_JMP 0x1000 // this group ends with an unconditional jump which is a candidate for removal
#ifdef TARGET_ARM64
#define IGF_HAS_REMOVED_INSTR 0x2000 // this group has an instruction that was removed.
#endif
// Mask of IGF_* flags that should be propagated to new blocks when they are created.
// This allows prologs and epilogs to be any number of IGs, but still be
// automatically marked properly.
#if defined(FEATURE_EH_FUNCLETS)
#ifdef DEBUG
#define IGF_PROPAGATE_MASK (IGF_EPILOG | IGF_FUNCLET_PROLOG | IGF_FUNCLET_EPILOG)
#else // DEBUG
#define IGF_PROPAGATE_MASK (IGF_EPILOG | IGF_FUNCLET_PROLOG)
#endif // DEBUG
#else // !FEATURE_EH_FUNCLETS
#define IGF_PROPAGATE_MASK (IGF_EPILOG)
#endif // !FEATURE_EH_FUNCLETS
// Try to do better packing based on how large regMaskSmall is (8, 16, or 64 bits).
CLANG_FORMAT_COMMENT_ANCHOR;
#if !(REGMASK_BITS <= 32)
regMaskSmall igGCregs; // set of registers with live GC refs
#endif // !(REGMASK_BITS <= 32)
union {
BYTE* igData; // addr of instruction descriptors
insPlaceholderGroupData* igPhData; // when igFlags & IGF_PLACEHOLDER
};
#if EMIT_BACKWARDS_NAVIGATION
// Last instruction in group, if any (nullptr if none); used for backwards navigation.
// (Should be type emitter::instrDesc*).
void* igLastIns;
#endif // EMIT_BACKWARDS_NAVIGATION
#if EMIT_TRACK_STACK_DEPTH
unsigned igStkLvl; // stack level on entry
#endif // EMIT_TRACK_STACK_DEPTH
#if REGMASK_BITS <= 32
regMaskSmall igGCregs; // set of registers with live GC refs
#endif // REGMASK_BITS <= 32
unsigned char igInsCnt; // # of instructions in this group
VARSET_VALRET_TP igGCvars() const
{
assert(igFlags & IGF_GC_VARS);
BYTE* ptr = (BYTE*)igData;
ptr -= sizeof(VARSET_TP);
return *(VARSET_TP*)ptr;
}
unsigned igByrefRegs() const
{
assert(igFlags & IGF_BYREF_REGS);
BYTE* ptr = (BYTE*)igData;
if (igFlags & IGF_GC_VARS)
{
ptr -= sizeof(VARSET_TP);
}
ptr -= sizeof(unsigned);
return *(unsigned*)ptr;
}
bool endsWithAlignInstr() const
{
return (igFlags & IGF_HAS_ALIGN) != 0;
}
// hadAlignInstr: Checks if this IG was ever marked as aligned and later
// decided to not align. Sometimes, a loop is marked as not
// needing alignment, but the igSize was not adjusted immediately.
// This method is used during loopSize calculation, where we adjust
// the loop size by removed alignment bytes.
bool hadAlignInstr() const
{
return (igFlags & IGF_REMOVED_ALIGN) != 0;
}
}; // end of struct insGroup
// For AMD64 the maximum prolog/epilog size supported on the OS is 256 bytes
// Since it is incorrect for us to be jumping across funclet prolog/epilogs
// we will use the following estimate as the maximum placeholder size.
//
#define MAX_PLACEHOLDER_IG_SIZE 256
#if defined(_MSC_VER) && defined(TARGET_ARM)
#pragma pack(pop)
#endif // defined(_MSC_VER) && defined(TARGET_ARM)
/*****************************************************************************/
#define DEFINE_ID_OPS
#include "emitfmts.h"
#undef DEFINE_ID_OPS
enum LclVarAddrTag
{
LVA_STANDARD_ENCODING = 0,
LVA_LARGE_OFFSET = 1,
LVA_COMPILER_TEMP = 2,
LVA_LARGE_VARNUM = 3
};
struct emitLclVarAddr
{
// Constructor
void initLclVarAddr(int varNum, unsigned offset);
int lvaVarNum(); // Returns the variable to access. Note that it returns a negative number for compiler spill temps.
unsigned lvaOffset(); // returns the offset into the variable to access
// This struct should be 32 bits in size for the release build.
// We have this constraint because this type is used in a union
// with several other pointer sized types in the instrDesc struct.
//
protected:
unsigned _lvaVarNum : 15; // Usually the lvaVarNum
unsigned _lvaExtra : 15; // Usually the lvaOffset
unsigned _lvaTag : 2; // tag field to support larger varnums
};
enum idAddrUnionTag
{
iaut_ALIGNED_POINTER = 0x0,
iaut_DATA_OFFSET = 0x1,
iaut_INST_COUNT = 0x2,
iaut_UNUSED_TAG = 0x3,
iaut_MASK = 0x3,
iaut_SHIFT = 2
};
class emitter
{
friend class emitLocation;
friend class Compiler;
friend class CodeGen;
friend class CodeGenInterface;
public:
/*************************************************************************
*
* Define the public entry points.
*/
// Constructor.
emitter()
{
#ifdef DEBUG
// There seem to be some cases where this is used without being initialized via CodeGen::inst_set_SV_var().
emitVarRefOffs = 0;
#endif // DEBUG
#ifdef TARGET_XARCH
SetUseVEXEncoding(false);
SetUseEvexEncoding(false);
#endif // TARGET_XARCH
emitDataSecCur = nullptr;
}
#include "emitpub.h"
protected:
/************************************************************************/
/* Miscellaneous stuff */
/************************************************************************/
Compiler* emitComp;
GCInfo* gcInfo;
CodeGen* codeGen;
size_t m_debugInfoSize;
typedef GCInfo::varPtrDsc varPtrDsc;
typedef GCInfo::regPtrDsc regPtrDsc;
typedef GCInfo::CallDsc callDsc;
void* emitGetMem(size_t sz);
enum opSize : unsigned
{
OPSZ1 = 0,
OPSZ2 = 1,
OPSZ4 = 2,
OPSZ8 = 3,
OPSZ16 = 4,
#if defined(TARGET_XARCH)
OPSZ32 = 5,
OPSZ64 = 6,
OPSZ_COUNT = 7,
#else
OPSZ_COUNT = 5,
#endif
#ifdef TARGET_AMD64
OPSZP = OPSZ8,
#else
OPSZP = OPSZ4,
#endif
};
#define OPSIZE_INVALID ((opSize)0xffff)
static const emitAttr emitSizeDecode[];
static emitter::opSize emitEncodeSize(emitAttr size);
static emitAttr emitDecodeSize(emitter::opSize ensz);
// Currently, we only allow one IG for the prolog
bool emitIGisInProlog(const insGroup* ig)
{
return ig == emitPrologIG;
}
bool emitIGisInEpilog(const insGroup* ig)
{
return (ig != nullptr) && ((ig->igFlags & IGF_EPILOG) != 0);
}
#if defined(FEATURE_EH_FUNCLETS)
bool emitIGisInFuncletProlog(const insGroup* ig)
{
return (ig != nullptr) && ((ig->igFlags & IGF_FUNCLET_PROLOG) != 0);
}
bool emitIGisInFuncletEpilog(const insGroup* ig)
{
return (ig != nullptr) && ((ig->igFlags & IGF_FUNCLET_EPILOG) != 0);
}
#endif // FEATURE_EH_FUNCLETS
// If "ig" corresponds to the start of a basic block that is the
// target of a funclet return, generate GC information for it's start
// address "cp", as if it were the return address of a call.
void emitGenGCInfoIfFuncletRetTarget(insGroup* ig, BYTE* cp);
void emitRecomputeIGoffsets();
void emitDispCommentForHandle(size_t handle, size_t cookie, GenTreeFlags flags);
/************************************************************************/
/* The following describes a single instruction */
/************************************************************************/
enum insFormat : unsigned
{
#define IF_DEF(en, op1, op2) IF_##en,
#include "emitfmts.h"
IF_COUNT
};
#ifdef TARGET_XARCH
#define AM_DISP_BITS ((sizeof(unsigned) * 8) - 2 * (REGNUM_BITS + 1) - 2)
#define AM_DISP_BIG_VAL (-(1 << (AM_DISP_BITS - 1)))
#define AM_DISP_MIN (-((1 << (AM_DISP_BITS - 1)) - 1))
#define AM_DISP_MAX (+((1 << (AM_DISP_BITS - 1)) - 1))
struct emitAddrMode
{
regNumber amBaseReg : REGNUM_BITS + 1;
regNumber amIndxReg : REGNUM_BITS + 1;
emitter::opSize amScale : 2;
int amDisp : AM_DISP_BITS;
};
#endif // TARGET_XARCH
struct instrDescDebugInfo
{
unsigned idNum;
size_t idSize; // size of the instruction descriptor
unsigned idVarRefOffs; // IL offset for LclVar reference
unsigned idVarRefOffs2; // IL offset for 2nd LclVar reference (in case this is a pair)
size_t idMemCookie; // compile time handle (check idFlags)
GenTreeFlags idFlags; // for determining type of handle in idMemCookie
bool idFinallyCall; // Branch instruction is a call to finally
bool idCatchRet; // Instruction is for a catch 'return'
CORINFO_SIG_INFO* idCallSig; // Used to report native call site signatures to the EE
};
#ifdef TARGET_ARM
unsigned insEncodeSetFlags(insFlags sf);
enum insSize : unsigned
{
ISZ_16BIT,
ISZ_32BIT,
ISZ_48BIT // pseudo-instruction for conditional branch with imm24 range,
// encoded as IT of condition followed by an unconditional branch
};
unsigned insEncodeShiftOpts(insOpts opt);
unsigned insEncodePUW_G0(insOpts opt, int imm);
unsigned insEncodePUW_H0(insOpts opt, int imm);
#endif // TARGET_ARM
struct instrDescCns;
struct instrDesc
{
private:
// The assembly instruction
#if defined(TARGET_XARCH)
static_assert_no_msg(INS_count <= 1024);
instruction _idIns : 10;
#define MAX_ENCODED_SIZE 15
#elif defined(TARGET_ARM64)
#define INSTR_ENCODED_SIZE 4
static_assert_no_msg(INS_count <= 512);
instruction _idIns : 9;
#elif defined(TARGET_LOONGARCH64)
// TODO-LoongArch64: not include SIMD-vector.
static_assert_no_msg(INS_count <= 512);
instruction _idIns : 9;
#else
static_assert_no_msg(INS_count <= 256);
instruction _idIns : 8;
#endif // !(defined(TARGET_XARCH) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64))
// The format for the instruction
#if defined(TARGET_XARCH)
static_assert_no_msg(IF_COUNT <= 128);
insFormat _idInsFmt : 7;
#elif defined(TARGET_LOONGARCH64)
unsigned _idCodeSize : 5; // the instruction(s) size of this instrDesc described.
#elif defined(TARGET_RISCV64)
unsigned _idCodeSize : 6; // the instruction(s) size of this instrDesc described.
#else
static_assert_no_msg(IF_COUNT <= 256);
insFormat _idInsFmt : 8;
#endif
public:
instrDesc() = delete; // Do not stack alloc this due to debug info that has to come before it.
instruction idIns() const
{
return _idIns;
}
void idIns(instruction ins)
{
assert((ins != INS_invalid) && (ins < INS_count));
_idIns = ins;
}
bool idInsIs(instruction ins) const
{
return idIns() == ins;
}
template <typename... T>
bool idInsIs(instruction ins, T... rest) const
{
return idInsIs(ins) || idInsIs(rest...);
}
#if defined(TARGET_LOONGARCH64)
insFormat idInsFmt() const
{ // not used for LOONGARCH64.
return (insFormat)0;
}
void idInsFmt(insFormat insFmt)
{
}
#elif defined(TARGET_RISCV64)
insFormat idInsFmt() const
{
NYI_RISCV64("idInsFmt-----unimplemented on RISCV64 yet----");
return (insFormat)0;
}
void idInsFmt(insFormat insFmt)
{
NYI_RISCV64("idInsFmt-----unimplemented on RISCV64 yet----");
}
#else
insFormat idInsFmt() const
{
return _idInsFmt;
}
void idInsFmt(insFormat insFmt)
{
#if defined(TARGET_ARM64)
noway_assert(insFmt != IF_NONE); // Only the x86 emitter uses IF_NONE, it is invalid for ARM64 (and ARM32)
#endif
assert(insFmt < IF_COUNT);
_idInsFmt = insFmt;
}
#endif
////////////////////////////////////////////////////////////////////////
// Space taken up to here:
// x86: 17 bits
// amd64: 17 bits
// arm: 16 bits
// arm64: 17 bits
// loongarch64: 14 bits
// risc-v: 14 bits
private:
#if defined(TARGET_XARCH)
unsigned _idCodeSize : 4; // size of instruction in bytes. Max size of an Intel instruction is 15 bytes.
opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16, 5=32
// At this point we have fully consumed first DWORD so that next field
// doesn't cross a byte boundary.
#elif defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
/* _idOpSize defined below. */
#else
opSize _idOpSize : 2; // operand size: 0=1 , 1=2 , 2=4 , 3=8
#endif // TARGET_ARM64 || TARGET_LOONGARCH64 || TARGET_RISCV64
// On Amd64, this is where the second DWORD begins
// On System V a call could return a struct in 2 registers. The instrDescCGCA struct below has member that
// stores the GC-ness of the second register.
// It is added to the instrDescCGCA and not here (the base struct) since it is not needed by all the
// instructions. This struct (instrDesc) is very carefully kept to be no more than 128 bytes. There is no more
// space to add members for keeping GC-ness of the second return registers. It will also bloat the base struct
// unnecessarily since the GC-ness of the second register is only needed for call instructions.
// The instrDescCGCA struct's member keeping the GC-ness of the first return register is _idcSecondRetRegGCType.
GCtype _idGCref : 2; // GCref operand? (value is a "GCtype")
// The idReg1 and idReg2 fields hold the first and second register
// operand(s), whenever these are present. Note that currently the
// size of these fields is 6 bits on all targets, and care needs to
// be taken to make sure all of these fields stay reasonably packed.
// Note that we use the _idReg1 and _idReg2 fields to hold
// the live gcrefReg mask for the call instructions on x86/x64
//
regNumber _idReg1 : REGNUM_BITS; // register num
regNumber _idReg2 : REGNUM_BITS;
////////////////////////////////////////////////////////////////////////
// Space taken up to here:
// x86: 38 bits
// amd64: 38 bits
// arm: 32 bits
// arm64: 31 bits
// loongarch64: 28 bits
// risc-v: 28 bits
unsigned _idSmallDsc : 1; // is this a "small" descriptor?
unsigned _idLargeCns : 1; // does a large constant follow?
unsigned _idLargeDsp : 1; // does a large displacement follow?
unsigned _idLargeCall : 1; // large call descriptor used
unsigned _idBound : 1; // jump target / frame offset bound
unsigned _idCallRegPtr : 1; // IL indirect calls: addr in reg
unsigned _idCallAddr : 1; // IL indirect calls: can make a direct call to iiaAddr
unsigned _idNoGC : 1; // Some helpers don't get recorded in GC tables
#if defined(TARGET_XARCH)
unsigned _idEvexbContext : 1; // does EVEX.b need to be set.
#endif // TARGET_XARCH
#ifdef TARGET_ARM64
opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16
insOpts _idInsOpt : 6; // options for instructions
unsigned _idLclVar : 1; // access a local on stack
unsigned _idLclVarPair : 1 // carries information for 2 GC lcl vars.
#endif
#ifdef TARGET_LOONGARCH64
// TODO-LoongArch64: maybe delete on future.
opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16
insOpts _idInsOpt : 6; // loongarch options for special: placeholders. e.g emitIns_R_C, also identifying the
// accessing a local on stack.
unsigned _idLclVar : 1; // access a local on stack.
#endif
#ifdef TARGET_RISCV64
// TODO-RISCV64: maybe delete on future
opSize _idOpSize : 3; // operand size: 0=1 , 1=2 , 2=4 , 3=8, 4=16
insOpts _idInsOpt : 6; // options for instructions
unsigned _idLclVar : 1; // access a local on stack
#endif
#ifdef TARGET_ARM
insSize _idInsSize : 2; // size of instruction: 16, 32 or 48 bits
insFlags _idInsFlags : 1; // will this instruction set the flags
unsigned _idLclVar : 1; // access a local on stack
unsigned _idLclFPBase : 1; // access a local on stack - SP based offset
insOpts _idInsOpt : 3; // options for Load/Store instructions
#endif
////////////////////////////////////////////////////////////////////////
// Space taken up to here:
// x86: 47 bits
// amd64: 47 bits
// arm: 48 bits
// arm64: 50 bits
// loongarch64: 46 bits
// risc-v: 46 bits
//
// How many bits have been used beyond the first 32?
// Define ID_EXTRA_BITFIELD_BITS to that number.
//
CLANG_FORMAT_COMMENT_ANCHOR;
#if defined(TARGET_ARM)
#define ID_EXTRA_BITFIELD_BITS (16)
#elif defined(TARGET_ARM64)
#define ID_EXTRA_BITFIELD_BITS (18)
#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
#define ID_EXTRA_BITFIELD_BITS (14)
#elif defined(TARGET_XARCH)
#define ID_EXTRA_BITFIELD_BITS (15)
#else
#error Unsupported or unset target architecture
#endif
unsigned _idCnsReloc : 1; // LargeCns is an RVA and needs reloc tag
unsigned _idDspReloc : 1; // LargeDsp is an RVA and needs reloc tag
#define ID_EXTRA_RELOC_BITS (2)
#if EMIT_BACKWARDS_NAVIGATION
// "Pointer" to previous instrDesc in this group. If zero, there is
// no previous instrDesc. If non-zero, then _idScaledPrevOffset * 4
// is the size in bytes of the previous instrDesc; subtract that from
// the current instrDesc* to reach the previous one.
// All instrDesc types are <= 56 bytes, but we also need m_debugInfoSize,
// which is pointer sized, so 5 bits are required on 64-bit and 4 bits
// on 32-bit.
CLANG_FORMAT_COMMENT_ANCHOR;
#ifdef HOST_64BIT
unsigned _idScaledPrevOffset : 5;
#define ID_EXTRA_PREV_OFFSET_BITS (5)
#else
unsigned _idScaledPrevOffset : 4;
#define ID_EXTRA_PREV_OFFSET_BITS (4)
#endif
#else // !EMIT_BACKWARDS_NAVIGATION
#define ID_EXTRA_PREV_OFFSET_BITS (0)
#endif // !EMIT_BACKWARDS_NAVIGATION
////////////////////////////////////////////////////////////////////////
// Space taken up to here (with/without prev offset, assuming host==target):
// x86: 53/49 bits
// amd64: 54/49 bits
// arm: 54/50 bits
// arm64: 57/52 bits
// loongarch64: 53/48 bits
// risc-v: 53/48 bits
CLANG_FORMAT_COMMENT_ANCHOR;
#define ID_EXTRA_BITS (ID_EXTRA_RELOC_BITS + ID_EXTRA_BITFIELD_BITS + ID_EXTRA_PREV_OFFSET_BITS)
/* Use whatever bits are left over for small constants */
#define ID_BIT_SMALL_CNS (32 - ID_EXTRA_BITS)
C_ASSERT(ID_BIT_SMALL_CNS > 0);
////////////////////////////////////////////////////////////////////////
// Small constant size (with/without prev offset, assuming host==target):
// x86: 11/15 bits
// amd64: 10/15 bits
// arm: 10/14 bits
// arm64: 7/12 bits
// loongarch64: 11/16 bits
// risc-v: 11/16 bits
CLANG_FORMAT_COMMENT_ANCHOR;
#define ID_ADJ_SMALL_CNS (int)(1 << (ID_BIT_SMALL_CNS - 1))
#define ID_CNT_SMALL_CNS (int)(1 << ID_BIT_SMALL_CNS)
#define ID_MIN_SMALL_CNS (int)(0 - ID_ADJ_SMALL_CNS)
#define ID_MAX_SMALL_CNS (int)(ID_CNT_SMALL_CNS - ID_ADJ_SMALL_CNS - 1)
// We encounter many constants, but there is a disproportionate amount that are in the range [-1, +4]
// and otherwise powers of 2. We therefore allow the tracked range here to include negative values.
signed _idSmallCns : ID_BIT_SMALL_CNS;
////////////////////////////////////////////////////////////////////////
// Space taken up to here: 64 bits, all architectures, by design.
////////////////////////////////////////////////////////////////////////
//
// This is the end of the 'small' instrDesc which is the same on all platforms
//
// If you add lots more fields that need to be cleared (such
// as various flags), you might need to update the body of
// emitter::emitAllocInstr() to clear them.
//
// SMALL_IDSC_SIZE is this size, in bytes.
//
CLANG_FORMAT_COMMENT_ANCHOR;
#define SMALL_IDSC_SIZE 8
public:
instrDescDebugInfo* idDebugOnlyInfo() const
{
const char* addr = reinterpret_cast<const char*>(this);
return *reinterpret_cast<instrDescDebugInfo* const*>(addr - sizeof(instrDescDebugInfo*));
}
void idDebugOnlyInfo(instrDescDebugInfo* info)
{
char* addr = reinterpret_cast<char*>(this);
*reinterpret_cast<instrDescDebugInfo**>(addr - sizeof(instrDescDebugInfo*)) = info;
}
private:
CLANG_FORMAT_COMMENT_ANCHOR;
void checkSizes();
union idAddrUnion {
// TODO-Cleanup: We should really add a DEBUG-only tag to this union so we can add asserts
// about reading what we think is here, to avoid unexpected corruption issues.
#if !defined(TARGET_ARM64) && !defined(TARGET_LOONGARCH64) && !defined(TARGET_RISCV64)
emitLclVarAddr iiaLclVar;
#endif
BasicBlock* iiaBBlabel;
insGroup* iiaIGlabel;
BYTE* iiaAddr;
#ifdef TARGET_XARCH
emitAddrMode iiaAddrMode;
#endif // TARGET_XARCH
CORINFO_FIELD_HANDLE iiaFieldHnd; // iiaFieldHandle is also used to encode
// an offset into the JIT data constant area
bool iiaIsJitDataOffset() const;
int iiaGetJitDataOffset() const;
// iiaEncodedInstrCount and its accessor functions are used to specify an instruction
// count for jumps, instead of using a label and multiple blocks. This is used in the
// prolog as well as for IF_LARGEJMP pseudo-branch instructions.
int iiaEncodedInstrCount;
bool iiaHasInstrCount() const
{
return (iiaEncodedInstrCount & iaut_MASK) == iaut_INST_COUNT;
}
int iiaGetInstrCount() const
{
assert(iiaHasInstrCount());
return (iiaEncodedInstrCount >> iaut_SHIFT);
}
void iiaSetInstrCount(int count)
{
assert(abs(count) < 10);
iiaEncodedInstrCount = (count << iaut_SHIFT) | iaut_INST_COUNT;
}
#ifdef TARGET_ARMARCH
struct
{
#ifdef TARGET_ARM64
// For 64-bit architecture this 32-bit structure can pack with these unsigned bit fields
emitLclVarAddr iiaLclVar;
unsigned _idReg3Scaled : 1; // Reg3 is scaled by idOpSize bits
GCtype _idGCref2 : 2;
#endif
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
};
#elif defined(TARGET_XARCH)
struct
{
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
};
#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
struct
{
unsigned int iiaEncodedInstr; // instruction's binary encoding.
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
};
struct
{
int iiaJmpOffset; // temporary saving the offset of jmp or data.
emitLclVarAddr iiaLclVar;
};