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hwintrinsiccodegenxarch.cpp
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hwintrinsiccodegenxarch.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Intel hardware intrinsic Code Generator XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifdef FEATURE_HW_INTRINSICS
#include "emit.h"
#include "codegen.h"
#include "sideeffects.h"
#include "lower.h"
#include "gcinfo.h"
#include "gcinfoencoder.h"
//------------------------------------------------------------------------
// assertIsContainableHWIntrinsicOp: Asserts that op is containable by node
//
// Arguments:
// lowering - The lowering phase from the compiler
// containingNode - The HWIntrinsic node that has the contained node
// containedNode - The node that is contained
//
static void assertIsContainableHWIntrinsicOp(Lowering* lowering,
GenTreeHWIntrinsic* containingNode,
GenTree* containedNode)
{
#if DEBUG
// The Lowering::IsContainableHWIntrinsicOp call is not quite right, since it follows pre-register allocation
// logic. However, this check is still important due to the various containment rules that SIMD intrinsics follow.
//
// We use isContainable to track the special HWIntrinsic node containment rules (for things like LoadAligned and
// LoadUnaligned) and we use the supportsRegOptional check to support general-purpose loads (both from stack
// spillage and for isUsedFromMemory contained nodes, in the case where the register allocator decided to not
// allocate a register in the first place).
GenTree* node = containedNode;
// Now that we are doing full memory containment safety checks, we can't properly check nodes that are not
// linked into an evaluation tree, like the special nodes we create in genHWIntrinsic.
// So, just say those are ok.
//
if (node->gtNext == nullptr)
{
return;
}
bool supportsRegOptional = false;
bool isContainable = lowering->IsContainableHWIntrinsicOp(containingNode, node, &supportsRegOptional);
assert(isContainable || supportsRegOptional);
#endif // DEBUG
}
//------------------------------------------------------------------------
// genIsTableDrivenHWIntrinsic:
//
// Arguments:
// category - category of a HW intrinsic
//
// Return Value:
// returns true if this category can be table-driven in CodeGen
//
static bool genIsTableDrivenHWIntrinsic(NamedIntrinsic intrinsicId, HWIntrinsicCategory category)
{
// TODO - make more categories to the table-driven framework
// HW_Category_Helper and HW_Flag_MultiIns/HW_Flag_SpecialCodeGen usually need manual codegen
const bool tableDrivenCategory =
(category != HW_Category_Special) && (category != HW_Category_Scalar) && (category != HW_Category_Helper);
const bool tableDrivenFlag =
!HWIntrinsicInfo::GeneratesMultipleIns(intrinsicId) && !HWIntrinsicInfo::HasSpecialCodegen(intrinsicId);
return tableDrivenCategory && tableDrivenFlag;
}
//------------------------------------------------------------------------
// AddEmbRoundingMode: Adds the embedded rounding mode to the insOpts
//
// Arguments:
// instOptions - The existing insOpts
// mode - The embedded rounding mode to add to instOptions
//
// Return Value:
// The modified insOpts
//
static insOpts AddEmbRoundingMode(insOpts instOptions, int8_t mode)
{
// The full rounding mode is a bitmask in the shape of:
// * RC: 2-bit rounding control
// * RS: 1-bit rounding select
// * P: 1-bit precision mask
// * 4-bit reserved
//
// The embedded rounding form assumes that P is 1, indicating
// that floating-point exceptions should not be raised and also
// assumes that RS is 0, indicating that MXCSR.RC is ignored.
//
// Given that the user is specifying a rounding mode and that
// .NET doesn't support raising IEEE 754 floating-point exceptions,
// we simplify the handling below to only consider the 2-bits of RC.
assert((instOptions & INS_OPTS_EVEX_b_MASK) == 0);
unsigned result = static_cast<unsigned>(instOptions);
switch (mode & 0x03)
{
case 0x01:
{
result |= INS_OPTS_EVEX_eb_er_rd;
break;
}
case 0x02:
{
result |= INS_OPTS_EVEX_er_ru;
break;
}
case 0x03:
{
result |= INS_OPTS_EVEX_er_rz;
break;
}
default:
{
break;
}
}
return static_cast<insOpts>(result);
}
//------------------------------------------------------------------------
// AddEmbMaskingMode: Adds the embedded masking mode to the insOpts
//
// Arguments:
// instOptions - The existing insOpts
// maskReg - The register to use for the embedded mask
// mergeWithZero - true if the mask merges with zero; otherwise, false
//
// Return Value:
// The modified insOpts
//
static insOpts AddEmbMaskingMode(insOpts instOptions, regNumber maskReg, bool mergeWithZero)
{
assert((instOptions & INS_OPTS_EVEX_aaa_MASK) == 0);
assert((instOptions & INS_OPTS_EVEX_z_MASK) == 0);
unsigned result = static_cast<unsigned>(instOptions);
unsigned em_k = (maskReg - KBASE) << 2;
unsigned em_z = mergeWithZero ? INS_OPTS_EVEX_em_zero : 0;
assert(emitter::isMaskReg(maskReg));
assert((em_k & INS_OPTS_EVEX_aaa_MASK) == em_k);
result |= em_k;
result |= em_z;
return static_cast<insOpts>(result);
}
//------------------------------------------------------------------------
// genHWIntrinsic: Generates the code for a given hardware intrinsic node.
//
// Arguments:
// node - The hardware intrinsic node
//
void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
NamedIntrinsic intrinsicId = node->GetHWIntrinsicId();
CORINFO_InstructionSet isa = HWIntrinsicInfo::lookupIsa(intrinsicId);
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsicId);
size_t numArgs = node->GetOperandCount();
GenTree* embMaskOp = nullptr;
// We need to validate that other phases of the compiler haven't introduced unsupported intrinsics
assert(compiler->compIsaSupportedDebugOnly(isa));
assert(HWIntrinsicInfo::RequiresCodegen(intrinsicId));
bool isTableDriven = genIsTableDrivenHWIntrinsic(intrinsicId, category);
insOpts instOptions = INS_OPTS_NONE;
if (GetEmitter()->UseEvexEncoding())
{
if (numArgs == 3)
{
GenTree* op2 = node->Op(2);
if (op2->IsEmbMaskOp())
{
assert(intrinsicId == NI_AVX512F_BlendVariableMask);
assert(op2->isContained());
assert(op2->OperIsHWIntrinsic());
// We currently only support this for table driven intrinsics
assert(isTableDriven);
GenTree* op1 = node->Op(1);
GenTree* op3 = node->Op(3);
regNumber targetReg = node->GetRegNum();
regNumber mergeReg = op1->GetRegNum();
regNumber maskReg = op3->GetRegNum();
// TODO-AVX512-CQ: Ensure we can support embedded operations on RMW intrinsics
assert(!op2->isRMWHWIntrinsic(compiler));
bool mergeWithZero = op1->isContained();
if (mergeWithZero)
{
// We're merging with zero, so we the target register isn't RMW
assert(op1->IsVectorZero());
mergeWithZero = true;
}
else
{
// We're merging with a non-zero value, so the target register is RMW
emitAttr attr = emitActualTypeSize(Compiler::getSIMDTypeForSize(node->GetSimdSize()));
GetEmitter()->emitIns_Mov(INS_movaps, attr, targetReg, mergeReg, /* canSkip */ true);
}
// Update op2 to use the actual target register
op2->ClearContained();
op2->SetRegNum(targetReg);
// Fixup all the already initialized variables
node = op2->AsHWIntrinsic();
intrinsicId = node->GetHWIntrinsicId();
isa = HWIntrinsicInfo::lookupIsa(intrinsicId);
category = HWIntrinsicInfo::lookupCategory(intrinsicId);
numArgs = node->GetOperandCount();
// Add the embedded masking info to the insOpts
instOptions = AddEmbMaskingMode(instOptions, maskReg, mergeWithZero);
// We don't need to genProduceReg(node) since that will be handled by processing op2
// likewise, processing op2 will ensure its own registers are consumed
// Make sure we consume the registers that are getting specially handled
genConsumeReg(op1);
embMaskOp = op3;
}
}
if (node->OperIsEmbRoundingEnabled())
{
GenTree* lastOp = node->Op(numArgs);
// Now that we've extracted the rounding mode, we'll remove the
// last operand, adjust the arg count, and continue. This allows
// us to reuse all the existing logic without having to add new
// specialized handling everywhere.
switch (numArgs)
{
case 2:
{
numArgs = 1;
node->ResetHWIntrinsicId(intrinsicId, compiler, node->Op(1));
break;
}
case 3:
{
numArgs = 2;
node->ResetHWIntrinsicId(intrinsicId, compiler, node->Op(1), node->Op(2));
break;
}
case 4:
{
numArgs = 3;
node->ResetHWIntrinsicId(intrinsicId, compiler, node->Op(1), node->Op(2), node->Op(3));
break;
}
default:
{
unreached();
}
}
if (lastOp->isContained())
{
assert(lastOp->IsCnsIntOrI());
int8_t mode = static_cast<int8_t>(lastOp->AsIntCon()->IconValue());
instOptions = AddEmbRoundingMode(instOptions, mode);
}
else
{
var_types baseType = node->GetSimdBaseType();
instruction ins = HWIntrinsicInfo::lookupIns(intrinsicId, baseType);
assert(ins != INS_invalid);
emitAttr simdSize = emitActualTypeSize(Compiler::getSIMDTypeForSize(node->GetSimdSize()));
assert(simdSize != 0);
genConsumeMultiOpOperands(node);
genConsumeRegs(lastOp);
if (isTableDriven)
{
switch (numArgs)
{
case 1:
{
regNumber targetReg = node->GetRegNum();
GenTree* rmOp = node->Op(1);
auto emitSwCase = [&](int8_t i) {
insOpts newInstOptions = AddEmbRoundingMode(instOptions, i);
genHWIntrinsic_R_RM(node, ins, simdSize, targetReg, rmOp, newInstOptions);
};
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, lastOp->GetRegNum(), baseReg, offsReg,
emitSwCase);
break;
}
case 2:
{
auto emitSwCase = [&](int8_t i) {
insOpts newInstOptions = AddEmbRoundingMode(instOptions, i);
genHWIntrinsic_R_R_RM(node, ins, simdSize, newInstOptions);
};
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, lastOp->GetRegNum(), baseReg, offsReg,
emitSwCase);
break;
}
default:
{
unreached();
}
}
}
else
{
// There are a few embedded rounding intrinsics that need to be emitted with special handling.
genNonTableDrivenHWIntrinsicsJumpTableFallback(node, lastOp);
}
genProduceReg(node);
return;
}
}
}
if (isTableDriven)
{
regNumber targetReg = node->GetRegNum();
var_types baseType = node->GetSimdBaseType();
GenTree* op1 = nullptr;
GenTree* op2 = nullptr;
GenTree* op3 = nullptr;
GenTree* op4 = nullptr;
regNumber op1Reg = REG_NA;
regNumber op2Reg = REG_NA;
regNumber op3Reg = REG_NA;
regNumber op4Reg = REG_NA;
emitter* emit = GetEmitter();
assert(numArgs >= 0);
instruction ins = HWIntrinsicInfo::lookupIns(intrinsicId, baseType);
assert(ins != INS_invalid);
emitAttr simdSize = emitActualTypeSize(Compiler::getSIMDTypeForSize(node->GetSimdSize()));
assert(simdSize != 0);
int ival = HWIntrinsicInfo::lookupIval(compiler, intrinsicId, baseType);
switch (numArgs)
{
case 1:
{
op1 = node->Op(1);
if (node->OperIsMemoryLoad())
{
genConsumeAddress(op1);
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_IND to generate code with.
GenTreeIndir load = indirForm(node->TypeGet(), op1);
emit->emitInsLoadInd(ins, simdSize, node->GetRegNum(), &load);
}
else
{
genConsumeRegs(op1);
op1Reg = op1->GetRegNum();
if (ival != -1)
{
assert((ival >= 0) && (ival <= 127));
if (HWIntrinsicInfo::CopiesUpperBits(intrinsicId))
{
assert(!op1->isContained());
emit->emitIns_SIMD_R_R_R_I(ins, simdSize, targetReg, op1Reg, op1Reg,
static_cast<int8_t>(ival));
}
else
{
genHWIntrinsic_R_RM_I(node, ins, simdSize, static_cast<int8_t>(ival));
}
}
else if (HWIntrinsicInfo::CopiesUpperBits(intrinsicId))
{
assert(!op1->isContained());
emit->emitIns_SIMD_R_R_R(ins, simdSize, targetReg, op1Reg, op1Reg);
}
else
{
genHWIntrinsic_R_RM(node, ins, simdSize, targetReg, op1, instOptions);
}
}
break;
}
case 2:
{
op1 = node->Op(1);
op2 = node->Op(2);
if (category == HW_Category_MemoryStore)
{
genConsumeAddress(op1);
genConsumeReg(op2);
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_STORE_IND to generate code with.
GenTreeStoreInd store = storeIndirForm(node->TypeGet(), op1, op2);
emit->emitInsStoreInd(ins, simdSize, &store);
break;
}
genConsumeRegs(op1);
genConsumeRegs(op2);
op1Reg = op1->GetRegNum();
op2Reg = op2->GetRegNum();
if ((op1Reg != targetReg) && (op2Reg == targetReg) && node->isRMWHWIntrinsic(compiler))
{
// We have "reg2 = reg1 op reg2" where "reg1 != reg2" on a RMW intrinsic.
//
// For non-commutative intrinsics, we should have ensured that op2 was marked
// delay free in order to prevent it from getting assigned the same register
// as target. However, for commutative intrinsics, we can just swap the operands
// in order to have "reg2 = reg2 op reg1" which will end up producing the right code.
noway_assert(node->OperIsCommutative());
op2Reg = op1Reg;
op1Reg = targetReg;
}
if (ival != -1)
{
assert((ival >= 0) && (ival <= 127));
genHWIntrinsic_R_R_RM_I(node, ins, simdSize, static_cast<int8_t>(ival));
}
else if (category == HW_Category_MemoryLoad)
{
// Get the address and the 'other' register.
GenTree* addr;
regNumber otherReg;
if (intrinsicId == NI_AVX_MaskLoad || intrinsicId == NI_AVX2_MaskLoad)
{
addr = op1;
otherReg = op2Reg;
}
else
{
addr = op2;
otherReg = op1Reg;
}
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_IND to generate code with.
GenTreeIndir load = indirForm(node->TypeGet(), addr);
assert(!node->isRMWHWIntrinsic(compiler));
inst_RV_RV_TT(ins, simdSize, targetReg, otherReg, &load, false, instOptions);
}
else if (HWIntrinsicInfo::isImmOp(intrinsicId, op2))
{
auto emitSwCase = [&](int8_t i) {
if (HWIntrinsicInfo::CopiesUpperBits(intrinsicId))
{
assert(!op1->isContained());
emit->emitIns_SIMD_R_R_R_I(ins, simdSize, targetReg, op1Reg, op1Reg, i);
}
else
{
genHWIntrinsic_R_RM_I(node, ins, simdSize, i);
}
};
if (op2->IsCnsIntOrI())
{
ssize_t ival = op2->AsIntCon()->IconValue();
assert((ival >= 0) && (ival <= 255));
emitSwCase((int8_t)ival);
}
else
{
// We emit a fallback case for the scenario when the imm-op is not a constant.
// This should
// normally happen when the intrinsic is called indirectly, such as via
// Reflection. However, it
// can also occur if the consumer calls it directly and just doesn't pass a
// constant value.
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, op2Reg, baseReg, offsReg, emitSwCase);
}
}
else if (node->TypeGet() == TYP_VOID)
{
genHWIntrinsic_R_RM(node, ins, simdSize, op1Reg, op2);
}
else
{
genHWIntrinsic_R_R_RM(node, ins, simdSize, instOptions);
}
break;
}
case 3:
{
op1 = node->Op(1);
op2 = node->Op(2);
op3 = node->Op(3);
genConsumeRegs(op1);
op1Reg = op1->GetRegNum();
genConsumeRegs(op2);
op2Reg = op2->GetRegNum();
genConsumeRegs(op3);
op3Reg = op3->GetRegNum();
assert(ival == -1);
if (HWIntrinsicInfo::isImmOp(intrinsicId, op3))
{
auto emitSwCase = [&](int8_t i) {
genHWIntrinsic_R_R_RM_I(node, ins, simdSize, i);
};
if (op3->IsCnsIntOrI())
{
ssize_t ival = op3->AsIntCon()->IconValue();
assert((ival >= 0) && (ival <= 255));
emitSwCase((int8_t)ival);
}
else
{
// We emit a fallback case for the scenario when the imm-op is not a constant. This should
// normally happen when the intrinsic is called indirectly, such as via Reflection. However, it
// can also occur if the consumer calls it directly and just doesn't pass a constant value.
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, op3Reg, baseReg, offsReg, emitSwCase);
}
}
else if (category == HW_Category_MemoryStore)
{
// The Mask instructions do not currently support containment of the address.
assert(!op2->isContained());
if (intrinsicId == NI_AVX_MaskStore || intrinsicId == NI_AVX2_MaskStore)
{
emit->emitIns_AR_R_R(ins, simdSize, op2Reg, op3Reg, op1Reg, 0);
}
else
{
assert(intrinsicId == NI_SSE2_MaskMove);
assert(targetReg == REG_NA);
// SSE2 MaskMove hardcodes the destination (op3) in DI/EDI/RDI
emit->emitIns_Mov(INS_mov, EA_PTRSIZE, REG_EDI, op3Reg, /* canSkip */ true);
emit->emitIns_R_R(ins, simdSize, op1Reg, op2Reg);
}
}
else
{
switch (intrinsicId)
{
case NI_SSE41_BlendVariable:
case NI_AVX_BlendVariable:
case NI_AVX2_BlendVariable:
case NI_AVX512F_BlendVariableMask:
{
genHWIntrinsic_R_R_RM_R(node, ins, simdSize);
break;
}
case NI_AVXVNNI_MultiplyWideningAndAdd:
case NI_AVXVNNI_MultiplyWideningAndAddSaturate:
{
assert(targetReg != REG_NA);
assert(op1Reg != REG_NA);
assert(op2Reg != REG_NA);
genHWIntrinsic_R_R_R_RM(ins, simdSize, targetReg, op1Reg, op2Reg, op3);
break;
}
default:
{
unreached();
break;
};
}
}
break;
}
case 4:
{
op1 = node->Op(1);
op2 = node->Op(2);
op3 = node->Op(3);
op4 = node->Op(4);
genConsumeRegs(op1);
op1Reg = op1->GetRegNum();
genConsumeRegs(op2);
op2Reg = op2->GetRegNum();
genConsumeRegs(op3);
op3Reg = op3->GetRegNum();
genConsumeRegs(op4);
op4Reg = op4->GetRegNum();
assert(ival == -1);
if (HWIntrinsicInfo::isImmOp(intrinsicId, op4))
{
auto emitSwCase = [&](int8_t i) {
genHWIntrinsic_R_R_R_RM_I(node, ins, simdSize, i);
};
if (op4->IsCnsIntOrI())
{
ssize_t ival = op4->AsIntCon()->IconValue();
assert((ival >= 0) && (ival <= 255));
emitSwCase(static_cast<int8_t>(ival));
}
else
{
// We emit a fallback case for the scenario when the imm-op is not a constant. This should
// normally happen when the intrinsic is called indirectly, such as via Reflection. However, it
// can also occur if the consumer calls it directly and just doesn't pass a constant value.
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, op4Reg, baseReg, offsReg, emitSwCase);
}
}
else
{
unreached();
}
break;
}
default:
unreached();
break;
}
if (embMaskOp != nullptr)
{
// Handle an extra operand we need to consume so that
// embedded masking can work without making the overall
// logic significantly more complex.
genConsumeReg(embMaskOp);
}
genProduceReg(node);
return;
}
assert(embMaskOp == nullptr);
switch (isa)
{
case InstructionSet_Vector128:
case InstructionSet_Vector256:
case InstructionSet_Vector512:
genBaseIntrinsic(node);
break;
case InstructionSet_X86Base:
case InstructionSet_X86Base_X64:
genX86BaseIntrinsic(node);
break;
case InstructionSet_SSE:
case InstructionSet_SSE_X64:
genSSEIntrinsic(node, instOptions);
break;
case InstructionSet_SSE2:
case InstructionSet_SSE2_X64:
genSSE2Intrinsic(node, instOptions);
break;
case InstructionSet_SSE41:
case InstructionSet_SSE41_X64:
genSSE41Intrinsic(node);
break;
case InstructionSet_SSE42:
case InstructionSet_SSE42_X64:
genSSE42Intrinsic(node);
break;
case InstructionSet_AVX:
case InstructionSet_AVX2:
case InstructionSet_AVX512F:
case InstructionSet_AVX512F_VL:
case InstructionSet_AVX512F_X64:
case InstructionSet_AVX512BW:
case InstructionSet_AVX512BW_VL:
case InstructionSet_AVX512VBMI:
case InstructionSet_AVX512VBMI_VL:
genAvxFamilyIntrinsic(node, instOptions);
break;
case InstructionSet_AES:
genAESIntrinsic(node);
break;
case InstructionSet_BMI1:
case InstructionSet_BMI1_X64:
case InstructionSet_BMI2:
case InstructionSet_BMI2_X64:
genBMI1OrBMI2Intrinsic(node, instOptions);
break;
case InstructionSet_FMA:
genFMAIntrinsic(node, instOptions);
break;
case InstructionSet_LZCNT:
case InstructionSet_LZCNT_X64:
genLZCNTIntrinsic(node);
break;
case InstructionSet_PCLMULQDQ:
genPCLMULQDQIntrinsic(node);
break;
case InstructionSet_POPCNT:
case InstructionSet_POPCNT_X64:
genPOPCNTIntrinsic(node);
break;
case InstructionSet_X86Serialize:
case InstructionSet_X86Serialize_X64:
genX86SerializeIntrinsic(node);
break;
default:
unreached();
break;
}
}
//------------------------------------------------------------------------
// genHWIntrinsic_R_RM: Generates code for a hardware intrinsic node that takes a
// register operand and a register/memory operand.
//
// Arguments:
// node - The hardware intrinsic node
// ins - The instruction being generated
// attr - The emit attribute for the instruction being generated
// reg - The register
// rmOp - The register/memory operand node
// instOptions - the existing intOpts
void CodeGen::genHWIntrinsic_R_RM(
GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, regNumber reg, GenTree* rmOp, insOpts instOptions)
{
emitter* emit = GetEmitter();
OperandDesc rmOpDesc = genOperandDesc(rmOp);
if (((instOptions & INS_OPTS_EVEX_b_MASK) != 0) && (rmOpDesc.GetKind() == OperandKind::Reg))
{
// As embedded rounding only appies in R_R case, we can skip other checks for different paths.
regNumber op1Reg = rmOp->GetRegNum();
assert(op1Reg != REG_NA);
emit->emitIns_R_R(ins, attr, reg, op1Reg, instOptions);
return;
}
if (rmOpDesc.IsContained())
{
assert(HWIntrinsicInfo::SupportsContainment(node->GetHWIntrinsicId()));
assertIsContainableHWIntrinsicOp(compiler->m_pLowering, node, rmOp);
}
switch (rmOpDesc.GetKind())
{
case OperandKind::ClsVar:
emit->emitIns_R_C(ins, attr, reg, rmOpDesc.GetFieldHnd(), 0);
break;
case OperandKind::Local:
emit->emitIns_R_S(ins, attr, reg, rmOpDesc.GetVarNum(), rmOpDesc.GetLclOffset());
break;
case OperandKind::Indir:
{
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_IND to generate code with.
GenTreeIndir indirForm;
GenTreeIndir* indir = rmOpDesc.GetIndirForm(&indirForm);
emit->emitIns_R_A(ins, attr, reg, indir);
}
break;
case OperandKind::Reg:
{
regNumber rmOpReg = rmOpDesc.GetReg();
if (emit->IsMovInstruction(ins))
{
emit->emitIns_Mov(ins, attr, reg, rmOpReg, /* canSkip */ false);
}
else
{
if (varTypeIsIntegral(rmOp))
{
bool needsBroadcastFixup = false;
bool needsInstructionFixup = false;
switch (node->GetHWIntrinsicId())
{
case NI_AVX2_BroadcastScalarToVector128:
case NI_AVX2_BroadcastScalarToVector256:
{
if (varTypeIsSmall(node->GetSimdBaseType()))
{
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512BW_VL))
{
needsInstructionFixup = true;
}
else
{
needsBroadcastFixup = true;
}
}
else if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F_VL))
{
needsInstructionFixup = true;
}
else
{
needsBroadcastFixup = true;
}
break;
}
case NI_AVX512F_BroadcastScalarToVector512:
case NI_AVX512BW_BroadcastScalarToVector512:
{
needsInstructionFixup = true;
break;
}
default:
{
break;
}
}
if (needsBroadcastFixup)
{
// In lowering we had the special case of BroadcastScalarToVector(CreateScalarUnsafe(op1))
//
// This is one of the only instructions where it supports taking integer types from
// a SIMD register or directly as a scalar from memory. Most other instructions, in
// comparison, take such values from general-purpose registers instead.
//
// Because of this, we removed the CreateScalarUnsafe and tried to contain op1 directly
// that failed and we either didn't get marked regOptional or we did and didn't get spilled
//
// As such, we need to emulate the removed CreateScalarUnsafe to ensure that op1 is in a
// SIMD register so the broadcast instruction can execute succesfully. We'll just move
// the value into the target register and then broadcast it out from that.
emitAttr movdAttr = emitActualTypeSize(node->GetSimdBaseType());
emit->emitIns_Mov(INS_movd, movdAttr, reg, rmOpReg, /* canSkip */ false);
rmOpReg = reg;
}
else if (needsInstructionFixup)
{
switch (ins)
{
case INS_vpbroadcastb:
{
ins = INS_vpbroadcastb_gpr;
break;
}
case INS_vpbroadcastd:
{
ins = INS_vpbroadcastd_gpr;
break;
}
case INS_vpbroadcastq:
{
ins = INS_vpbroadcastq_gpr;
break;
}
case INS_vpbroadcastw:
{
ins = INS_vpbroadcastw_gpr;
break;
}
default:
{
unreached();
}
}
}
}
emit->emitIns_R_R(ins, attr, reg, rmOpReg);
}
break;
}
default:
unreached();
}
}
//------------------------------------------------------------------------
// genHWIntrinsic_R_RM_I: Generates the code for a hardware intrinsic node that takes a register/memory operand,
// an immediate operand, and that returns a value in register
//
// Arguments:
// node - The hardware intrinsic node
// ins - The instruction being generated
// ival - The immediate value
//
void CodeGen::genHWIntrinsic_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, emitAttr simdSize, int8_t ival)
{
regNumber targetReg = node->GetRegNum();
GenTree* op1 = node->Op(1);
// TODO-XArch-CQ: Commutative operations can have op1 be contained
// TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
assert(targetReg != REG_NA);
assert(!node->OperIsCommutative()); // One operand intrinsics cannot be commutative
if (op1->isContained() || op1->isUsedFromSpillTemp())
{
assert(HWIntrinsicInfo::SupportsContainment(node->GetHWIntrinsicId()));
assertIsContainableHWIntrinsicOp(compiler->m_pLowering, node, op1);
}
inst_RV_TT_IV(ins, simdSize, targetReg, op1, ival);
}
//------------------------------------------------------------------------
// genHWIntrinsic_R_R_RM: Generates the code for a hardware intrinsic node that takes a register operand, a
// register/memory operand, and that returns a value in register
//
// Arguments:
// node - The hardware intrinsic node
// ins - The instruction being generated
// attr - The emit attribute for the instruction being generated
// instOptions - The options that modify how the instruction is generated
//
void CodeGen::genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, insOpts instOptions)
{
regNumber targetReg = node->GetRegNum();
GenTree* op1 = node->Op(1);
GenTree* op2 = node->Op(2);
regNumber op1Reg = op1->GetRegNum();
assert(targetReg != REG_NA);
assert(op1Reg != REG_NA);
if (op2->isContained() || op2->isUsedFromSpillTemp())
{
assert(HWIntrinsicInfo::SupportsContainment(node->GetHWIntrinsicId()));
assertIsContainableHWIntrinsicOp(compiler->m_pLowering, node, op2);