[Arm64] ASIMD InsertScalar

[echesakov]

These were omitted from #35037

class AdvSimd.Arm64
{
  // float64x2_t vcopyq_lane_f64 (float64x2_t a, const int lane1, float64x1_t b, const int lane2)
  //   A64: INS Vd.D[lane1], Vn.D[0]
  public static Vector128<double> InsertScalar(Vector128<double> result, byte resultIndex, Vector64<double> value);

  // int64x2_t vcopyq_lane_s64 (int64x2_t a, const int lane1, int64x1_t b, const int lane2)
  //   A64: INS Vd.D[lane1], Vn.D[0]
  public static Vector128<long> InsertScalar(Vector128<long> result, byte resultIndex, Vector64<long> value);

  // uint64x2_t vcopyq_lane_u64 (uint64x2_t a, const int lane1, uint64x1_t b, const int lane2)
  //   A64: INS Vd.D[lane1], Vn.D[0]
  public static Vector128<ulong> InsertScalar(Vector128<ulong> result, byte resultIndex, Vector64<ulong> value);
}

Motivation:
These would allow to implement Vector128.WithLower() as

AdvSimd.Arm64.InsertScalar(vector.AsUInt64(), 0, value.AsUInt64()).As<ulong, T>();

and Vector128.WithUpper() as

AdvSimd.InsertScalar(vector.AsUInt64(), 1, value.AsUInt64()).As<ulong, T>();

cc @CarolEidt @tannergooding @TamarChristinaArm

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[TamarChristinaArm]

Semantically speaking these intrinsics are implementable on Arm32 with a single instruction, They are all mov.I64 D{d,d+1},Dn.

We don't have them for A32 in ACLE because we don't define some of these x1_t types for AArch32.

[terrajobst]

Video

namespace System.Runtime.Intrinsics.Arm
{
    public static class AdvSimd
    {
        public static Vector128<double> InsertScalar(Vector128<double> result, byte resultIndex, Vector64<double> value);
        public static Vector128<long>   InsertScalar(Vector128<long>   result, byte resultIndex, Vector64<long>   value);
        public static Vector128<ulong>  InsertScalar(Vector128<ulong>  result, byte resultIndex, Vector64<ulong>  value);
    }
}

[echesakov]

Semantically speaking these intrinsics are implementable on Arm32 with a single instruction, They are all mov.I64 D{d,d+1},Dn.

We don't have them for A32 in ACLE because we don't define some of these x1_t types for AArch32.

@TamarChristinaArm I meant to reply earlier on your message, but forgot. Thanks for your feedback! I will place the intrinsics under AdvSimd and alter the comment showing how to implement this on A32.