JIT: Control-flow guard checked calls should preference call target to validator-preserved register

[jakobbotsch]

Description

We currently see an unnecessary reg-reg mov for the call target when CFG enabled code is generated. Usually only happens on arm64 because on x64 the register that the validator takes the target in is rcx and so conflicts with the first argument anyway.

Reproduction Steps

$env:COMPlus_TieredCompilation=0
$env:COMPlus_JitForceControlFlowGuard=1

[MethodImpl(MethodImplOptions.NoInlining)]
public static void M(I i)
{
    i.Foo();
}

We produce the following code:

G_M6547_IG02:              ;; offset=0008H
        D280010F          movz    x15, #8
        F2B9218F          movk    x15, #0xc90c LSL #16
        F2CFFFCF          movk    x15, #0x7ffe LSL #32
        F94001EF          ldr     x15, [x15]
        94000000          bl      CORINFO_HELP_VALIDATE_INDIRECT_CALL
        AA0F03E1          mov     x1, x15
        D280010B          movz    x11, #8
        F2B9218B          movk    x11, #0xc90c LSL #16
        F2CFFFCB          movk    x11, #0x7ffe LSL #32
        D63F0020          blr     x1

Expected behavior

G_M6547_IG02:              ;; offset=0008H
         D280010F          movz    x15, #8
         F2B9218F          movk    x15, #0xc90c LSL #16
         F2CFFFCF          movk    x15, #0x7ffe LSL #32
         F94001EF          ldr     x15, [x15]
         94000000          bl      CORINFO_HELP_VALIDATE_INDIRECT_CALL
-        AA0F03E1          mov     x1, x15
         D280010B          movz    x11, #8
         F2B9218B          movk    x11, #0xc90c LSL #16
         F2CFFFCB          movk    x11, #0x7ffe LSL #32
-        D63F0020          blr     x1
+        D63F0020          blr     x15

Actual behavior

No unnecessary reg-reg mov.

Regression?

No response

Known Workarounds

No response

Configuration

No response

Other information

No response

category:cq
theme:register-allocator

[jakobbotsch]

@kunalspathak This is the issue I spoke to you about last week.

[ghost]

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Issue Details

---

Description

We currently see an unnecessary reg-reg mov for the call target when CFG enabled code is generated. Usually only happens on arm64 because on x64 the register that the validator takes the target in is rcx and so conflicts with the first argument anyway.

Reproduction Steps

$env:COMPlus_TieredCompilation=0
$env:COMPlus_JitForceControlFlowGuard=1

[MethodImpl(MethodImplOptions.NoInlining)]
public static void M(I i)
{
    i.Foo();
}

We produce the following code:

G_M6547_IG02:              ;; offset=0008H
        D280010F          movz    x15, #8
        F2B9218F          movk    x15, #0xc90c LSL #16
        F2CFFFCF          movk    x15, #0x7ffe LSL #32
        F94001EF          ldr     x15, [x15]
        94000000          bl      CORINFO_HELP_VALIDATE_INDIRECT_CALL
        AA0F03E1          mov     x1, x15
        D280010B          movz    x11, #8
        F2B9218B          movk    x11, #0xc90c LSL #16
        F2CFFFCB          movk    x11, #0x7ffe LSL #32
        D63F0020          blr     x1

Expected behavior

G_M6547_IG02:              ;; offset=0008H
        D280010F          movz    x15, #8
        F2B9218F          movk    x15, #0xc90c LSL #16
        F2CFFFCF          movk    x15, #0x7ffe LSL #32
        F94001EF          ldr     x15, [x15]
        94000000          bl      CORINFO_HELP_VALIDATE_INDIRECT_CALL
        D280010B          movz    x11, #8
        F2B9218B          movk    x11, #0xc90c LSL #16
        F2CFFFCB          movk    x11, #0x7ffe LSL #32
        D63F0020          blr     x15

Actual behavior

No unnecessary reg-reg mov.

Regression?

No response

Known Workarounds

No response

Configuration

No response

Other information

No response

Author:	jakobbotsch
Assignees:	-
Labels:	arch-arm64, area-CodeGen-coreclr, untriaged
Milestone:	-