Skip to content
Avatar
Block or Report

Block or report dschaefer

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. Project template for FPGA dev

    SystemVerilog

  2. fpga-bounce Public

    Example fpga bounce with Yosys simulation.

    SystemVerilog

  3. Adder example written in VHDL

    VHDL

15 contributions in the last year

Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Mon Wed Fri

Contribution activity

July 1, 2022

dschaefer has no activity yet for this period.

Seeing something unexpected? Take a look at the GitHub profile guide.