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ALU.sv
ALU.sv
 
 
MUX_ALUSrc.sv
MUX_ALUSrc.sv
 
 
MUX_MemtoReg.sv
MUX_MemtoReg.sv
 
 
MUX_RegDst.sv
MUX_RegDst.sv
 
 
PC.sv
PC.sv
 
 
README.md
README.md
 
 
data_memory.sv
data_memory.sv
 
 
instruction_memory.sv
instruction_memory.sv
 
 
register_file.sv
register_file.sv
 
 
sign_extend.sv
sign_extend.sv
 
 
testbench.sv
testbench.sv
 
 

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A single-cycle CPU using a subset of a RISC-based instruction set. Written in SystemVerilog on Quartus. Below is an image of the resulting waveforms obtained using ModelSim.

ex

exa

todo

Add instructions. Make it multi-cycle. Add pipelining.

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