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bcm63xx: fix USB base registers and IRQs for BCM6328
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33005 3c298f89-4303-0410-b956-a3cf2f4a3e73
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Aug 5, 2012
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target/linux/brcm63xx/patches-3.3/107-MIPS-BCM63XX-Fix-USB-IRQ-definitions-for-6328.patch
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@@ -0,0 +1,26 @@ | ||
From 960e1ef3c5b2d69a4a5a6984b6408d65221dd86c Mon Sep 17 00:00:00 2001 | ||
From: Kevin Cernekee <cernekee@gmail.com> | ||
Date: Sat, 23 Jun 2012 04:14:55 +0000 | ||
Subject: [PATCH 06/81] MIPS: BCM63XX: Fix USB IRQ definitions for 6328 | ||
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||
OHCI/EHCI are in the high (second) word. Not currently used by any | ||
driver. | ||
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||
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> | ||
--- | ||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 4 ++-- | ||
1 file changed, 2 insertions(+), 2 deletions(-) | ||
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | ||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | ||
@@ -602,8 +602,8 @@ enum bcm63xx_irq { | ||
#define BCM_6328_ENET0_IRQ 0 | ||
#define BCM_6328_ENET1_IRQ 0 | ||
#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) | ||
-#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) | ||
-#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) | ||
+#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) | ||
+#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) | ||
#define BCM_6328_PCMCIA_IRQ 0 | ||
#define BCM_6328_ENET0_RXDMA_IRQ 0 | ||
#define BCM_6328_ENET0_TXDMA_IRQ 0 |
62 changes: 62 additions & 0 deletions
62
target/linux/brcm63xx/patches-3.3/108-BCM63XX-Add-register-definitions-for-USBD-depen.patch
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@@ -0,0 +1,62 @@ | ||
From 21bb8141c205ae48d331787debb6b272add90ac7 Mon Sep 17 00:00:00 2001 | ||
From: Kevin Cernekee <cernekee@gmail.com> | ||
Date: Sat, 23 Jun 2012 04:14:54 +0000 | ||
Subject: [PATCH 05/81] MIPS: BCM63XX: Add register definitions for USBD | ||
dependencies | ||
|
||
The USB 2.0 device depends on some functionality in other blocks, such | ||
as GPIO and USBH. Add those register definitions here. | ||
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||
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> | ||
--- | ||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 6 +++--- | ||
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 8 ++++++++ | ||
2 files changed, 11 insertions(+), 3 deletions(-) | ||
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | ||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | ||
@@ -184,9 +184,9 @@ enum bcm63xx_regs_set { | ||
#define BCM_6328_SPI_BASE (0xdeadbeef) | ||
#define BCM_6328_UDC0_BASE (0xdeadbeef) | ||
#define BCM_6328_USBDMA_BASE (0xdeadbeef) | ||
-#define BCM_6328_OHCI0_BASE (0xdeadbeef) | ||
+#define BCM_6328_OHCI0_BASE (0xb0002600) | ||
#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) | ||
-#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef) | ||
+#define BCM_6328_USBH_PRIV_BASE (0xb0002700) | ||
#define BCM_6328_MPI_BASE (0xdeadbeef) | ||
#define BCM_6328_PCMCIA_BASE (0xdeadbeef) | ||
#define BCM_6328_PCIE_BASE (0xb0e40000) | ||
@@ -199,7 +199,7 @@ enum bcm63xx_regs_set { | ||
#define BCM_6328_ENETDMAC_BASE (0xb000da00) | ||
#define BCM_6328_ENETDMAS_BASE (0xb000dc00) | ||
#define BCM_6328_ENETSW_BASE (0xb0e00000) | ||
-#define BCM_6328_EHCI0_BASE (0x10002500) | ||
+#define BCM_6328_EHCI0_BASE (0xb0002500) | ||
#define BCM_6328_SDRAM_BASE (0xdeadbeef) | ||
#define BCM_6328_MEMC_BASE (0xdeadbeef) | ||
#define BCM_6328_DDR_BASE (0xb0003000) | ||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | ||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | ||
@@ -543,6 +543,12 @@ | ||
#define GPIO_MODE_6368_SPI_SSN5 (1 << 31) | ||
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+#define GPIO_PINMUX_OTHR_REG 0x24 | ||
+#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 | ||
+#define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | ||
+#define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | ||
+#define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | ||
+ | ||
#define GPIO_BASEMODE_6368_REG 0x38 | ||
#define GPIO_BASEMODE_6368_UART2 0x1 | ||
#define GPIO_BASEMODE_6368_GPIO 0x0 | ||
@@ -770,6 +776,8 @@ | ||
#define USBH_PRIV_SWAP_6358_REG 0x0 | ||
#define USBH_PRIV_SWAP_6368_REG 0x1c | ||
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||
+#define USBH_PRIV_SWAP_USBD_SHIFT 6 | ||
+#define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) | ||
#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 | ||
#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) | ||
#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 |
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