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llvm: Update baseline to e400e908b2d97529b1a65dd0bdad80d481c39527
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Showing 424 changed files with 1,722 additions and 1,606 deletions.
2 changes: 1 addition & 1 deletion llvm/llvm-project
Submodule llvm-project updated 68 files
+0 −1 clang/lib/Serialization/ASTWriter.cpp
+1 −1 libcxx/modules/std.compat/cstdlib.inc
+21 −0 lldb/docs/conf.py
+1 −0 lldb/docs/index.rst
+0 −2,286 lldb/docs/lldb-gdb-remote.txt
+2,399 −0 lldb/docs/resources/lldbgdbremote.md
+2 −2 llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp
+3 −9 llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp
+9 −0 llvm/include/llvm/TargetParser/CMakeLists.txt
+3 −1 llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
+0 −1 llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+3 −55 llvm/lib/Target/AArch64/AArch64Subtarget.h
+2 −1 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+5 −2 llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2 −1 llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+0 −4 llvm/lib/Target/ARM/ARMSubtarget.cpp
+6 −76 llvm/lib/Target/ARM/ARMSubtarget.h
+3 −0 llvm/lib/Target/RISCV/RISCV.h
+109 −17 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+3 −0 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2 −0 llvm/lib/TargetParser/CMakeLists.txt
+29 −0 llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+4 −0 llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+47 −16 llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
+4 −0 llvm/test/CodeGen/RISCV/O0-pipeline.ll
+1 −0 llvm/test/CodeGen/RISCV/O3-pipeline.ll
+651 −0 llvm/test/CodeGen/RISCV/rvv/commutable.ll
+2 −2 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+2 −2 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
+4 −4 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
+4 −4 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
+16 −16 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+331 −306 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+6 −6 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+3 −3 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
+14 −14 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+28 −28 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
+3 −3 llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+6 −6 llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+112 −64 llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+30 −42 llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
+30 −42 llvm/test/CodeGen/RISCV/rvv/vmfge.ll
+30 −42 llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
+30 −42 llvm/test/CodeGen/RISCV/rvv/vmfle.ll
+30 −42 llvm/test/CodeGen/RISCV/rvv/vmflt.ll
+30 −42 llvm/test/CodeGen/RISCV/rvv/vmfne.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmseq.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsge.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsle.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmslt.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
+44 −62 llvm/test/CodeGen/RISCV/rvv/vmsne.ll
+8 −8 llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+1 −1 llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
+37 −0 llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll
+19 −0 llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll
+17 −0 llvm/test/CodeGen/SPIRV/types/or-i1.ll
+162 −0 llvm/test/Transforms/InstCombine/add4.ll
+63 −0 llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+1 −0 llvm/utils/TableGen/CMakeLists.txt
+1 −28 utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+4 −1 utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
+49 −0 utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
+4 −1 utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl
4 changes: 2 additions & 2 deletions result/rvv/010f5d7f2e6c68c1.S
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Original file line number Diff line number Diff line change
Expand Up @@ -55,9 +55,9 @@ func0000000000000038: # @func0000000000000038
ret
func000000000000002a: # @func000000000000002a
vsetivli zero, 4, e64, m2, ta, mu
vmv.v.i v14, 1
vmsle.vi v0, v10, -1
vmv.v.i v10, 1
vsll.vv v8, v10, v12, v0.t
vsll.vv v8, v14, v12, v0.t
ret
func0000000000000034: # @func0000000000000034
vsetivli zero, 4, e64, m2, ta, ma
Expand Down
7 changes: 3 additions & 4 deletions result/rvv/0317a9ed6f365ed6.S
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Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
func0000000000000011: # @func0000000000000011
vsetivli zero, 4, e64, m2, ta, mu
vmv.v.i v12, 0
vmseq.vi v14, v8, 1
vmerge.vim v8, v12, 1, v0
vmv1r.v v0, v14
vadd.vv v12, v8, v10, v0.t
vmerge.vim v14, v12, 1, v0
vmseq.vi v0, v8, 1
vadd.vv v12, v14, v10, v0.t
vmv.v.v v8, v12
ret
15 changes: 8 additions & 7 deletions result/rvv/031ac0902fc367be.S
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Original file line number Diff line number Diff line change
Expand Up @@ -2,19 +2,20 @@ func0000000000000038: # @func0000000000000038
vsetivli zero, 4, e64, m2, ta, mu
vmv.v.i v10, 0
vmerge.vim v10, v10, 1, v0
vsll.vi v10, v10, 3
li a0, -2
zext.w a0, a0
vmsgtu.vx v0, v8, a0
vsll.vi v8, v10, 3
vadd.vi v8, v8, 8, v0.t
vadd.vi v10, v10, 8, v0.t
vmv.v.v v8, v10
ret
func0000000000000031: # @func0000000000000031
vsetivli zero, 16, e8, m1, ta, mu
vmv.v.i v10, 3
vmseq.vi v9, v8, 1
vmerge.vim v8, v10, 5, v0
vmv.v.v v0, v9
vadd.vi v8, v8, 2, v0.t
vmv.v.i v9, 3
vmerge.vim v9, v9, 5, v0
vmseq.vi v0, v8, 1
vadd.vi v9, v9, 2, v0.t
vmv.v.v v8, v9
ret
func0000000000000036: # @func0000000000000036
vsetivli zero, 8, e32, m2, ta, ma
Expand Down
4 changes: 2 additions & 2 deletions result/rvv/03e773af4a1ad86b.S
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
func0000000000000011: # @func0000000000000011
li a0, 10
vsetivli zero, 4, e64, m2, ta, mu
vmax.vx v12, v10, a0
vmseq.vv v0, v8, v10
vmax.vx v10, v10, a0
vadd.vi v8, v10, -10, v0.t
vadd.vi v8, v12, -10, v0.t
ret
4 changes: 2 additions & 2 deletions result/rvv/03e9c9210bc17885.S
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ func000000000000000a: # @func000000000000000a
ret
func0000000000000001: # @func0000000000000001
vsetivli zero, 8, e16, m1, ta, mu
vnsrl.wi v12, v10, 1
vmseq.vi v0, v9, 0
vnsrl.wi v9, v10, 1
vadd.vi v8, v9, 1, v0.t
vadd.vi v8, v12, 1, v0.t
ret
16 changes: 7 additions & 9 deletions result/rvv/041c4b5b20118268.S
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Original file line number Diff line number Diff line change
@@ -1,23 +1,21 @@
func0000000000000038: # @func0000000000000038
vmv1r.v v16, v0
fmv.w.x fa5, zero
vsetivli zero, 16, e32, m4, ta, mu
vmfge.vf v16, v12, fa5
vmnot.m v16, v16
vmv1r.v v17, v0
vmv1r.v v0, v16
vmfge.vf v17, v12, fa5
vmnot.m v0, v17
vfneg.v v12, v12, v0.t
vmv1r.v v0, v17
vmv1r.v v0, v16
vmerge.vvm v8, v8, v12, v0
vmfeq.vf v0, v8, fa5
ret
func0000000000000028: # @func0000000000000028
vmv1r.v v16, v0
fmv.w.x fa5, zero
vsetivli zero, 16, e32, m4, ta, mu
vmflt.vf v16, v12, fa5
vmv1r.v v17, v0
vmv1r.v v0, v16
vmflt.vf v0, v12, fa5
vfneg.v v12, v12, v0.t
vmv1r.v v0, v17
vmv1r.v v0, v16
vmerge.vvm v8, v8, v12, v0
vmfeq.vf v0, v8, fa5
ret
4 changes: 2 additions & 2 deletions result/rvv/045d8405931b8c91.S
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
func0000000000000069: # @func0000000000000069
vsetivli zero, 4, e64, m2, ta, mu
vsub.vv v12, v10, v12
vmsgt.vi v0, v10, 0
vsub.vv v10, v10, v12
vadd.vv v8, v8, v10, v0.t
vadd.vv v8, v8, v12, v0.t
ret
5 changes: 3 additions & 2 deletions result/rvv/047e2a9535747c0d.S
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Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,10 @@ func0000000000000008: # @func0000000000000008
func0000000000000004: # @func0000000000000004
li a0, 128
vsetivli zero, 4, e64, m2, ta, mu
vmv.v.x v14, a0
vmsltu.vv v0, v8, v10
vmv.v.x v8, a0
vminu.vx v8, v12, a0, v0.t
vminu.vx v14, v12, a0, v0.t
vmv.v.v v8, v14
ret
func0000000000000001: # @func0000000000000001
vsetivli zero, 4, e8, mf4, ta, ma
Expand Down
2 changes: 1 addition & 1 deletion result/rvv/065b9d398c746b86.S
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
func0000000000000008: # @func0000000000000008
li a0, 96
vsetivli zero, 4, e64, m2, ta, mu
vmsgtu.vi v0, v8, 8
vmv.v.x v10, a0
vmsgtu.vi v0, v8, 8
vadd.vx v10, v8, a0, v0.t
vmv.v.v v8, v10
ret
Expand Down
10 changes: 5 additions & 5 deletions result/rvv/06a41570d22bde49.S
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Original file line number Diff line number Diff line change
Expand Up @@ -65,11 +65,11 @@ func0000000000000034: # @func0000000000000034
ret
func000000000000003a: # @func000000000000003a
vsetivli zero, 8, e32, m2, ta, mu
vor.vi v14, v10, 4
vmsgt.vi v12, v8, 0
vmerge.vvm v8, v14, v10, v0
vmv1r.v v0, v12
vor.vi v8, v8, 8, v0.t
vor.vi v12, v10, 4
vmerge.vvm v10, v12, v10, v0
vmsgt.vi v0, v8, 0
vor.vi v10, v10, 8, v0.t
vmv.v.v v8, v10
ret
func000000000000000a: # @func000000000000000a
li a0, 64
Expand Down
5 changes: 3 additions & 2 deletions result/rvv/06c892443731bb66.S
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,8 @@ func0000000000000001: # @func0000000000000001
func0000000000000006: # @func0000000000000006
fli.s fa5, 0.5
vsetivli zero, 8, e32, m2, ta, mu
vfmul.vf v10, v10, fa5
vmsle.vi v0, v8, -1
vfmul.vf v8, v10, fa5
vfneg.v v8, v8, v0.t
vfneg.v v10, v10, v0.t
vmv.v.v v8, v10
ret
7 changes: 3 additions & 4 deletions result/rvv/0701739858065243.S
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Original file line number Diff line number Diff line change
Expand Up @@ -43,12 +43,11 @@ func000000000000002b: # @func000000000000002b
vor.vi v8, v8, 8, v0.t
ret
func0000000000000007: # @func0000000000000007
vmv1r.v v12, v0
vsetivli zero, 8, e32, m2, ta, mu
vmseq.vi v12, v10, 0
vmv1r.v v10, v0
vmv1r.v v0, v12
vmseq.vi v0, v10, 0
vor.vi v8, v8, 4, v0.t
vmv1r.v v0, v10
vmv1r.v v0, v12
vor.vi v8, v8, 2, v0.t
ret
func0000000000000010: # @func0000000000000010
Expand Down
8 changes: 4 additions & 4 deletions result/rvv/08f23e6f91ccddca.S
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Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
func00000000000000c1: # @func00000000000000c1
vsetivli zero, 4, e32, m1, ta, mu
vnsrl.wi v12, v10, 0
vmseq.vi v0, v9, 0
vnsrl.wi v9, v10, 0
vadd.vi v8, v9, 1, v0.t
vadd.vi v8, v12, 1, v0.t
ret
func0000000000000041: # @func0000000000000041
vsetivli zero, 8, e16, m1, ta, mu
vnsrl.wi v12, v10, 0
vmseq.vi v0, v9, 0
vnsrl.wi v9, v10, 0
vadd.vi v8, v9, -1, v0.t
vadd.vi v8, v12, -1, v0.t
ret
6 changes: 3 additions & 3 deletions result/rvv/09a0a940e045e0dc.S
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Original file line number Diff line number Diff line change
Expand Up @@ -18,10 +18,10 @@ func0000000000000014: # @func0000000000000014
func000000000000001c: # @func000000000000001c
li a0, 1792
vsetivli zero, 8, e32, m2, ta, mu
vmv.v.x v14, a0
vmseq.vi v0, v10, 0
vmv.v.x v10, a0
vand.vx v10, v12, a0, v0.t
vmsne.vv v0, v10, v8
vand.vx v14, v12, a0, v0.t
vmsne.vv v0, v14, v8
ret
func0000000000000044: # @func0000000000000044
bseti a0, zero, 11
Expand Down
2 changes: 1 addition & 1 deletion result/rvv/09e61c88b3a1e901.S
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
func0000000000000011: # @func0000000000000011
vsetivli zero, 4, e64, m2, ta, mu
vmseq.vi v0, v8, 0
vsub.vv v10, v10, v12
vmseq.vi v0, v8, 0
vsra.vi v8, v10, 3, v0.t
ret
4 changes: 2 additions & 2 deletions result/rvv/0a9932857fc1f748.S
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
func0000000000000111: # @func0000000000000111
li a0, 10
vsetivli zero, 4, e64, m2, ta, mu
vmax.vx v14, v12, a0
vmseq.vv v0, v10, v12
vmax.vx v12, v12, a0
vadd.vi v10, v12, -10, v0.t
vadd.vi v10, v14, -10, v0.t
vmseq.vv v0, v10, v8
ret
7 changes: 3 additions & 4 deletions result/rvv/0ae00c6959a67590.S
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Expand Up @@ -3,16 +3,15 @@
.LCPI0_1:
.word 0x40c90fdb # float 6.28318548
func0000000000000022: # @func0000000000000022
vmv1r.v v16, v0
lui a0, %hi(.LCPI0_0)
flw fa5, %lo(.LCPI0_0)(a0)
lui a0, %hi(.LCPI0_1)
flw fa4, %lo(.LCPI0_1)(a0)
vsetivli zero, 16, e32, m4, ta, mu
vmflt.vf v16, v12, fa5
vmv1r.v v17, v0
vmv1r.v v0, v16
vmflt.vf v0, v12, fa5
vfadd.vf v12, v12, fa4, v0.t
vmv1r.v v0, v17
vmv1r.v v0, v16
vmerge.vvm v8, v12, v8, v0
fmv.w.x fa5, zero
vmflt.vf v0, v8, fa5
Expand Down
4 changes: 2 additions & 2 deletions result/rvv/0ae32ca78d8f2e14.S
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Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
func0000000000000034: # @func0000000000000034
lui a0, 4096
vsetivli zero, 4, e64, m2, ta, mu
vmsltu.vx v0, v8, a0
vadd.vx v10, v8, a0
vmsltu.vx v0, v8, a0
vadd.vv v10, v8, v8, v0.t
vmv.v.v v8, v10
ret
func0000000000000004: # @func0000000000000004
lui a0, 256
vsetivli zero, 4, e64, m2, ta, mu
vmsltu.vx v0, v8, a0
vadd.vx v10, v8, a0
vmsltu.vx v0, v8, a0
vadd.vv v10, v8, v8, v0.t
vmv.v.v v8, v10
ret
4 changes: 2 additions & 2 deletions result/rvv/0c326e05669c777b.S
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ func0000000000000190: # @func0000000000000190
lui a0, 32
vsetivli zero, 4, e64, m2, ta, mu
vrsub.vx v12, v10, a0
vsrl.vi v12, v12, 11
vmsltu.vx v0, v10, a0
vsrl.vi v10, v12, 11
vadd.vv v8, v8, v10, v0.t
vadd.vv v8, v8, v12, v0.t
ret
4 changes: 2 additions & 2 deletions result/rvv/0c451975ecee5e19.S
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Original file line number Diff line number Diff line change
Expand Up @@ -7,19 +7,19 @@ func0000000000000001: # @func0000000000000001
.LCPI1_0:
.quad 0x3ce0000000000000 # double 1.7763568394002505E-15
func0000000000000003: # @func0000000000000003
vsetivli zero, 16, e64, m8, ta, mu
lui a0, %hi(.LCPI1_0)
fld fa5, %lo(.LCPI1_0)(a0)
vsetivli zero, 16, e64, m8, ta, mu
vfabs.v v16, v16
vfabs.v v16, v8, v0.t
vfmul.vf v8, v16, fa5
ret
.LCPI2_0:
.quad 0x3d00000000000000 # double 7.1054273576010019E-15
func0000000000000000: # @func0000000000000000
vsetivli zero, 16, e64, m8, ta, mu
lui a0, %hi(.LCPI2_0)
fld fa5, %lo(.LCPI2_0)(a0)
vsetivli zero, 16, e64, m8, ta, mu
vfabs.v v16, v16
vfabs.v v16, v8, v0.t
vfmul.vf v8, v16, fa5
Expand Down
5 changes: 3 additions & 2 deletions result/rvv/0dec912dde8b47d8.S
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
func0000000000000001: # @func0000000000000001
vsetivli zero, 4, e64, m2, ta, mu
vsext.vf2 v12, v10
vmseq.vi v0, v8, 0
vsext.vf2 v8, v10
vzext.vf2 v8, v10, v0.t
vzext.vf2 v12, v10, v0.t
vmv.v.v v8, v12
ret
5 changes: 3 additions & 2 deletions result/rvv/0e0dde71a9bbf719.S
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Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,9 @@ func0000000000000011: # @func0000000000000011
ret
func0000000000000014: # @func0000000000000014
vsetivli zero, 8, e32, m2, ta, mu
vxor.vi v10, v10, 7
li a0, 32
vmsltu.vx v0, v8, a0
vxor.vi v8, v10, 7
vor.vi v8, v8, 8, v0.t
vor.vi v10, v10, 8, v0.t
vmv.v.v v8, v10
ret
2 changes: 1 addition & 1 deletion result/rvv/0e2e8100fb96d3e5.S
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
func0000000000000026: # @func0000000000000026
vsetivli zero, 8, e32, m2, ta, mu
vmv.v.i v10, 1
li a0, 32
vmslt.vx v0, v8, a0
vmv.v.i v10, 1
vsll.vv v10, v10, v8, v0.t
vmv.v.v v8, v10
ret
Expand Down
2 changes: 1 addition & 1 deletion result/rvv/0ea9d5bdfbc51708.S
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@
.quad 0xc0bf400000000000 # double -8000
func0000000000000042: # @func0000000000000042
vsetivli zero, 16, e64, m8, ta, ma
vmand.mm v0, v0, v16
lui a0, %hi(.LCPI0_0)
fld fa5, %lo(.LCPI0_0)(a0)
vmand.mm v0, v0, v16
lui a0, %hi(.LCPI0_1)
fld fa4, %lo(.LCPI0_1)(a0)
vfmerge.vfm v8, v8, fa5, v0
Expand Down
24 changes: 12 additions & 12 deletions result/rvv/0eb5e95ad0350cc5.S
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@@ -1,36 +1,36 @@
.LCPI0_0:
.quad 0x3cc0000000000000 # double 4.4408920985006262E-16
func0000000000000014: # @func0000000000000014
fli.d fa5, min
lui a0, %hi(.LCPI0_0)
fld fa5, %lo(.LCPI0_0)(a0)
fli.d fa4, min
fld fa4, %lo(.LCPI0_0)(a0)
vsetivli zero, 16, e64, m8, ta, mu
vfmv.v.f v24, fa4
vfmul.vf v24, v16, fa5, v0.t
vfmv.v.f v24, fa5
vfmul.vf v24, v16, fa4, v0.t
vfabs.v v8, v8
vmflt.vv v0, v24, v8
ret
.LCPI1_0:
.quad 0x3cb0000000000000 # double 2.2204460492503131E-16
func0000000000000012: # @func0000000000000012
fli.d fa5, min
lui a0, %hi(.LCPI1_0)
fld fa5, %lo(.LCPI1_0)(a0)
fli.d fa4, min
fld fa4, %lo(.LCPI1_0)(a0)
vsetivli zero, 16, e64, m8, ta, mu
vfmv.v.f v24, fa4
vfmul.vf v24, v16, fa5, v0.t
vfmv.v.f v24, fa5
vfmul.vf v24, v16, fa4, v0.t
vfabs.v v8, v8
vmflt.vv v0, v8, v24
ret
.LCPI2_0:
.quad 0x3cc0000000000000 # double 4.4408920985006262E-16
func0000000000000004: # @func0000000000000004
fli.d fa5, min
lui a0, %hi(.LCPI2_0)
fld fa5, %lo(.LCPI2_0)(a0)
fli.d fa4, min
fld fa4, %lo(.LCPI2_0)(a0)
vsetivli zero, 16, e64, m8, ta, mu
vfmv.v.f v24, fa4
vfmul.vf v24, v16, fa5, v0.t
vfmv.v.f v24, fa5
vfmul.vf v24, v16, fa4, v0.t
vfabs.v v8, v8
vmflt.vv v0, v24, v8
ret
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