Skip to content
View du6293's full-sized avatar
🍓
I may be slow to respond.
🍓
I may be slow to respond.
2 followers · 3 following
Block or Report

Block or report du6293

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. IDEC IDEC Public

    Verilog design training using Intel FPGA organized by IDEC.

    Verilog

  2. pipeline_processor_c pipeline_processor_c Public

    RISC-V 5-stage pipeline cpu C

    C

  3. pipeline_processor_systemverilog pipeline_processor_systemverilog Public

    RISC-V pipeline processor with system verilog

    SystemVerilog

  4. single_cycle_processor_c single_cycle_processor_c Public

    RISC-V single-cycle-processor with C

    C 1

  5. single_cycle_processor_systemverilog single_cycle_processor_systemverilog Public

    RISC-V single-cycle-processor with system verilog

    SystemVerilog 1

  6. GPGPU-Sim GPGPU-Sim Public

    gpu emulation architecture simulaton

    Dockerfile