This repository hosts a series of patches implementing a (currently incomplete) RISC-V backend for LLVM. See the initial RFC for more about the implementation approach being taken with this port.
Our intent is that development and code review primarily occurs upstream on LLVM infrastructure. However, there is value is maintaining the RISC-V backend implementation as a set of clean patches. These will be continually rebased with the intention that they provide a useful reference for anybody starting a new LLVM backend or who wants to better understand backend implementation.
Patches are being submitted for review and eventual merging in to upstream LLVM. A number of patches laying the foundation for basic code generation have recently been published.
As well as the obvious implementation tasks, it is also our intent to augment this patchset with copious documentation. The primary author (Alex Bradbury, lowRISC CIC) has detailed notes that need to be cleaned up to form the basis of this.
Our aim is that RISC-V is the cleanest and most documented LLVM backend. As well as benefiting the wider LLVM community, this will make it substantially easier for research groups and hobbyists to explore hardware/software co-design with RISC-V.
Our lowRISC project is working to produce a completely open source System-on-Chip implementing the RISC-V instruction set architecture. One of the features we are pursuing is tagged memory. This repository will eventually host compiler support for that feature, although this may need time to mature before being ready to upstream and so may be developed in a separate branch.
All patches are under the LLVM license.