figured out picojpeg llvm problem...linker script and .data

picojpeg/Makefile

@@ -28,7 +28,7 @@ clean :
 #ARMGNU = arm-none-linux-gnueabi
 ARMGNU = arm-none-eabi
 
-COPS = -Wall -O2 -mthumb -nostdlib -nostartfiles -ffreestanding 
+COPS = -Wall -O3 -mthumb -nostdlib -nostartfiles -ffreestanding 
 AOPS = --warn --fatal-warnings
 
 
@@ -88,21 +88,4 @@ lpicojpegtest.bin : memmap vectors.o putget.o embedded.bc picojpegtest.bc picojp
 	$(ARMGNU)-objcopy lpicojpegtest.elf -O binary lpicojpegtest.bin 
 
 
-xpicojpegtest.bin : memmap vectors.o putget.o embedded.bc picojpegtest.bc picojpeg.bc uart.bc
-	#opt $(OOPS) embedded.bc -o embedded.opt.bc
-	#opt $(OOPS) picojpeg.bc -o picojpeg.opt.bc
-	#opt $(OOPS) picojpegtest.bc -o picojpegtest.opt.bc
-	#opt $(OOPS) uart.bc -o uart.opt.bc
-	#llc $(LLCOPS) embedded.opt.bc -filetype obj -o xembedded.o
-	llc $(LLCOPS) picojpeg.bc -filetype obj -o xpicojpeg.o
-	#llc $(LLCOPS) picojpegtest.opt.bc -filetype obj -o xpicojpegtest.o
-	#llc $(LLCOPS) uart.opt.bc -filetype obj -o xuart.o
-	llvm-link embedded.bc picojpegtest.bc uart.bc -o xpicojpegtest.raw.bc
-	opt $(OOPS) xpicojpegtest.raw.bc -o xpicojpegtest.bc
-	llc $(LLCOPS) xpicojpegtest.bc -filetype obj -o xpicojpegtest.o
-	#$(ARMGNU)-ld -T memmap vectors.o putget.o xembedded.o xpicojpeg.o xpicojpegtest.o xuart.o -o xpicojpegtest.elf
-	$(ARMGNU)-ld -T memmap vectors.o putget.o xpicojpegtest.o xpicojpeg.o -o xpicojpegtest.elf
-	$(ARMGNU)-objdump -D xpicojpegtest.elf > xpicojpegtest.list
-	$(ARMGNU)-objcopy xpicojpegtest.elf -O binary xpicojpegtest.bin 
-
 

picojpeg/README

@@ -22,7 +22,94 @@ have the lsbit set.  I have a few places where I trap for this waiting
 for a compiler to generate those instructions.  I removed the trap and
 the program worked fine.
 
-At the moment the llvm optimized build does not work with thumbulator
-I believe this is a thumbulator problem as it compiles and runs on
-real ARM hardware but so far not an apples to apples comparison.  I am
-using llvm 3.3 (seem my build_gcc repo, the build_clang script).
+The llvm optimized code was doing something with .data and I dont mess
+with .data so it was failing until I got the linker script and such just
+right.
+
+So this is a comparison between llvm and gcc llvm is using less
+instructions, more read cycles, fewer write cycles.  Overall fewer
+instructions but more memory cycles than gcc.
+
+Using -O3 optimizations on gcc it uses less everything, instructions,
+reads, writes.
+
+./thumbulator picojpeg/lpicojpegtest.bin
+00D3C870
+
+
+swi 0x01
+
+
+instructions 26254542
+fetches      26254542
+reads        12803264
+writes       7501769
+memcycles    46559575
+systick_ints 0
+
+
+-O2 optimizations:
+
+./thumbulator picojpeg/gpicojpegtest.bin
+00D3C870
+
+
+swi 0x01
+
+
+instructions 26612966
+fetches      26612966
+reads        9707188
+writes       6069420
+memcycles    42389574
+systick_ints 0
+
+
+-O3 optmizations:
+
+../thumbulator gpicojpegtest.bin
+00D3C870
+
+
+swi 0x01
+
+
+instructions 24468869
+fetches      24468869
+reads        6636744
+writes       3174541
+memcycles    34280154
+systick_ints 0
+
+
+
+
+
+
+
+
+
+
+clang --version
+clang version 3.3 (branches/release_33 185429)
+
+llc  --version
+LLVM (http://llvm.org/):
+  LLVM version 3.3
+  Optimized build with assertions.
+
+arm-none-eabi-gcc --version
+
+arm-none-eabi-gcc (GCC) 4.7.2
+Copyright (C) 2012 Free Software Foundation, Inc.
+This is free software; see the source for copying conditions.  There is NO
+warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+arm-none-eabi-as --version
+
+GNU assembler (GNU Binutils) 2.22
+Copyright 2011 Free Software Foundation, Inc.
+This program is free software; you may redistribute it under the terms of
+the GNU General Public License version 3 or later.
+This program has absolutely no warranty.
+This assembler was configured for a target of `arm-none-eabi'.

picojpeg/memmap

@@ -1,13 +1,13 @@
 /* memmap */
 MEMORY
 {
-    rom(RX)   : ORIGIN = 0x00000000, LENGTH = 0x00100000
-    ram(WAIL) : ORIGIN = 0x40000000, LENGTH = 0x00100000
+    rom : ORIGIN = 0x00000000, LENGTH = 0x00100000
+    ram : ORIGIN = 0x40000000, LENGTH = 0x00100000
 }
 
 SECTIONS
 {
     .text : { *(.text*) } > rom
-    .data : { *(.data*) } > ram
+    .bss : { *(.bss*) } > ram
 }
 

thumbulator.c

@@ -311,7 +311,14 @@ unsigned int read_register ( unsigned int reg )
 if(DBUG) fprintf(stderr,"read_register(%u)=",reg);
 if(DBUGREG) fprintf(stderr,"read_register(%u)=",reg);
     data=reg_norm[reg];
-    if(reg==15) data&=~1;
+    if(reg==15)
+    {
+        if(data&1)
+        {
+            fprintf(stderr,"pc has lsbit set 0x%08X\n",data);
+        }
+        data&=~1;
+    }
 if(DBUG) fprintf(stderr,"0x%08X\n",data);
 if(DBUGREG) fprintf(stderr,"0x%08X\n",data);
     return(data);
@@ -465,7 +472,7 @@ int execute ( void )
     inst=fetch16(pc-2);
     pc+=2;
     write_register(15,pc);
-if(DISS) fprintf(stderr,"0x%08X: 0x%04X ",(pc-4),inst);
+if(DISS) fprintf(stderr,"--- 0x%08X: 0x%04X ",(pc-4),inst);
 
 if(output_vcd)
 {
@@ -963,6 +970,7 @@ if(DISS) fprintf(stderr,"blx r%u\n",rm);
         if(rc&1)
         {
             write_register(14,(pc-2)|1);
+            rc&=~1;
             write_register(15,rc);
             return(0);
         }
@@ -983,6 +991,7 @@ if(DISS) fprintf(stderr,"bx r%u\n",rm);
 //fprintf(stderr,"bx r%u 0x%X 0x%X\n",rm,rc,pc);
         if(rc&1)
         {
+            rc&=~1;
             write_register(15,rc);
             return(0);
         }
@@ -1455,7 +1464,7 @@ if(DISS) fprintf(stderr,"mov r%u,r%u\n",rd,rm);
         if((rd==14)&&(rm==15))
         {
             //printf("mov lr,pc warning 0x%08X\n",pc-2);
-            rc|=1;
+            //rc|=1;
         }
         if(rd==15)
         {
@@ -1571,6 +1580,7 @@ if(DISS)
             {
                 fprintf(stderr,"pop {rc} with an ARM address pc 0x%08X popped 0x%08X\n",pc,rc);
                 //exit(1);
+                rc&=~1;
             }
             rc+=2;
             write_register(15,rc);
@@ -2061,9 +2071,15 @@ int reset ( void )
     handler_mode=0;
     cpsr=0;
 
-    reg_norm[13]=fetch32(0x00000000); //cortex-m3
+    reg_norm[13]=fetch32(0x00000000); //cortex-m
     reg_norm[14]=0xFFFFFFFF;
-    reg_norm[15]=fetch32(0x00000004); //cortex-m3
+    reg_norm[15]=fetch32(0x00000004); //cortex-m
+    if((reg_norm[15]&1)==0)
+    {
+        fprintf(stderr,"reset vector with an ARM address 0x%08X\n",reg_norm[15]);
+        exit(1);
+    }
+    reg_norm[15]&=~1;
     reg_norm[15]+=2;
 
     instructions=0;