Skip to content

Commit

Permalink
fix compiler warning for unused parameter and unused variable for cdna2
Browse files Browse the repository at this point in the history
  • Loading branch information
@bbiiggppiigg
bbiiggppiigg committed Nov 30, 2022
1 parent 8e1e20b commit 0620c22
Show file tree
Hide file tree
Showing 2 changed files with 82 additions and 82 deletions.
82 changes: 41 additions & 41 deletions instructionAPI/src/AMDGPU/cdna2/decodeOperands.C
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ACCVGPR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size){
switch(input){
case 512 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size);
case 513 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size);
Expand Down Expand Up @@ -259,7 +259,7 @@ case 767 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ATTR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ATTR(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::attr0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::attr1,0,opr_size);
Expand Down Expand Up @@ -297,34 +297,34 @@ case 32 : return makeRegisterExpression(amdgpu_cdna2::attr32,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_all,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size){
switch(input){
case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size);
case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PARAM(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PARAM(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::p10,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::p20,0,opr_size);
case 2 : return makeRegisterExpression(amdgpu_cdna2::p0,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PC(uint64_t input,uint32_t){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PC(uint64_t input, uint32_t ){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::pc_all);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -456,20 +456,20 @@ case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_EXEC(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size){
switch(input){
case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size);
case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_M0(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size){
switch(input){
case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SGPR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SGPR(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -576,7 +576,7 @@ case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SMEM_OFFSET(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SMEM_OFFSET(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -706,7 +706,7 @@ case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -1193,7 +1193,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_ACCVGPR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size){
switch(input){
case 768 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size);
case 769 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size);
Expand Down Expand Up @@ -1454,7 +1454,7 @@ case 1023 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLDS(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -1941,7 +1941,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLIT(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -2427,7 +2427,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_SIMPLE(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -2913,7 +2913,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size){
switch(input){
case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size);
case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size);
Expand Down Expand Up @@ -3174,7 +3174,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size){
switch(input){
case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size);
case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size);
Expand Down Expand Up @@ -3691,7 +3691,7 @@ case 1023 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size){
switch(input){
case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size);
case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size);
Expand Down Expand Up @@ -4298,7 +4298,7 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494));
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -4427,7 +4427,7 @@ case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG_NOVCC(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -4554,7 +4554,7 @@ case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -4785,7 +4785,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_0_63_INLINES(uint64_t input,uint32_t){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t ){
switch(input){
case 128 : return Immediate::makeImmediate(Result(u32, 0));
case 129 : return Immediate::makeImmediate(Result(u32, 1));
Expand Down Expand Up @@ -4854,7 +4854,7 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63));
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_INLINES(uint64_t input,uint32_t){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_INLINES(uint64_t input, uint32_t ){
switch(input){
case 128 : return Immediate::makeImmediate(Result(u32, 0));
case 129 : return Immediate::makeImmediate(Result(u32, 1));
Expand Down Expand Up @@ -4949,7 +4949,7 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494));
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_LANESEL(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -5143,7 +5143,7 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63));
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_NOLIT(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size);
Expand Down Expand Up @@ -5373,7 +5373,7 @@ case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size){
switch(input){
case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size);
case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size);
Expand All @@ -5382,19 +5382,19 @@ case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_s
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size){
switch(input){
case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size){
switch(input){
case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size){
switch(input){
case 128 : return Immediate::makeImmediate(Result(u32, 0));
case 129 : return Immediate::makeImmediate(Result(u32, 1));
Expand Down Expand Up @@ -5497,25 +5497,25 @@ case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size){
switch(input){
case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size){
switch(input){
case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size){
switch(input){
case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TGT(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TGT(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::mrt0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::mrt1,0,opr_size);
Expand Down Expand Up @@ -5566,7 +5566,7 @@ case 63 : return makeRegisterExpression(amdgpu_cdna2::param31,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TRAP(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TRAP(uint64_t input, uint32_t opr_size){
switch(input){
case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size);
case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size);
Expand All @@ -5587,20 +5587,20 @@ case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC(uint64_t input,uint32_t){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC(uint64_t input, uint32_t ){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::vcc);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC_LOHI(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size){
switch(input){
case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size);
case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size);
Expand Down Expand Up @@ -5861,7 +5861,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size){
switch(input){
case 0 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size);
case 1 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size);
Expand Down Expand Up @@ -6378,7 +6378,7 @@ case 767 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_LDS(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size){
switch(input){
case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size);
case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size);
Expand Down Expand Up @@ -6639,7 +6639,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size);
default: return makeRegisterExpression(amdgpu_cdna2::invalid);
}
}
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_XNACK_MASK_LOHI(uint64_t input,uint32_t opr_size ){
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size){
switch(input){
case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size);
case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size);
Expand Down

0 comments on commit 0620c22

Please sign in to comment.