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remove legacy register vector types
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@bbiiggppiigg
bbiiggppiigg committed Oct 3, 2023
1 parent da0609e commit 0e6103c
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Showing 3 changed files with 1 addition and 947 deletions.
30 changes: 0 additions & 30 deletions common/h/dyn_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1571,17 +1571,7 @@ namespace Dyninst
//0xff000000 0x00ff0000 0x0000ff00 0x000000ff
//arch reg cat:GPR alias&subrange reg ID
const signed int SGPR = 0x00010000;
const signed int SGPR_VEC2 = 0x00020000;
const signed int SGPR_VEC4 = 0x00030000;
const signed int SGPR_VEC8 = 0x00040000;
const signed int SGPR_VEC16 = 0x00050000;

const signed int VGPR = 0x00060000;
const signed int VGPR_VEC2 = 0x00070000;
const signed int VGPR_VEC4 = 0x00080000;
const signed int VGPR_VEC8 = 0x00090000;
const signed int VGPR_VEC16 = 0x000A0000;

const signed int ACC_VGPR = 0x000B0000;

const signed int HWR = 0x000C0000;
Expand Down Expand Up @@ -1785,17 +1775,7 @@ namespace Dyninst
//0xff000000 0x00ff0000 0x0000ff00 0x000000ff
//arch reg cat:GPR alias&subrange reg ID
const signed int SGPR = 0x00010000;
const signed int SGPR_VEC2 = 0x00020000;
const signed int SGPR_VEC4 = 0x00030000;
const signed int SGPR_VEC8 = 0x00040000;
const signed int SGPR_VEC16 = 0x00050000;

const signed int VGPR = 0x00060000;
const signed int VGPR_VEC2 = 0x00070000;
const signed int VGPR_VEC4 = 0x00080000;
const signed int VGPR_VEC8 = 0x00090000;
const signed int VGPR_VEC16 = 0x000A0000;

const signed int ACC_VGPR = 0x000B0000;

const signed int HWR = 0x000C0000;
Expand Down Expand Up @@ -1997,17 +1977,7 @@ namespace Dyninst
//0xff000000 0x00ff0000 0x0000ff00 0x000000ff
//arch reg cat:GPR alias&subrange reg ID
const signed int SGPR = 0x00010000;
const signed int SGPR_VEC2 = 0x00020000;
const signed int SGPR_VEC4 = 0x00030000;
const signed int SGPR_VEC8 = 0x00040000;
const signed int SGPR_VEC16 = 0x00050000;

const signed int VGPR = 0x00060000;
const signed int VGPR_VEC2 = 0x00070000;
const signed int VGPR_VEC4 = 0x00080000;
const signed int VGPR_VEC8 = 0x00090000;
const signed int VGPR_VEC16 = 0x000A0000;

const signed int ACC_VGPR = 0x000B0000;

const signed int HWR = 0x000C0000;
Expand Down
50 changes: 1 addition & 49 deletions common/src/dyn_regs.C
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Original file line number Diff line number Diff line change
Expand Up @@ -92,16 +92,8 @@ MachRegister MachRegister::getBaseRegister() const {
case Arch_amdgpu_gfx908:
switch (category){
case amdgpu_gfx908::SGPR:
case amdgpu_gfx908::SGPR_VEC2:
case amdgpu_gfx908::SGPR_VEC4:
case amdgpu_gfx908::SGPR_VEC8:
case amdgpu_gfx908::SGPR_VEC16:
return MachRegister( (reg & 0x000000ff) | amdgpu_gfx908::s0);
case amdgpu_gfx908::VGPR:
case amdgpu_gfx908::VGPR_VEC2:
case amdgpu_gfx908::VGPR_VEC4:
case amdgpu_gfx908::VGPR_VEC8:
case amdgpu_gfx908::VGPR_VEC16:
return MachRegister( (reg & 0x000000ff) | amdgpu_gfx908::v0);
case amdgpu_gfx908::HWR:
return MachRegister(reg);
Expand All @@ -113,16 +105,8 @@ MachRegister MachRegister::getBaseRegister() const {
case Arch_amdgpu_gfx90a:
switch (category){
case amdgpu_gfx90a::SGPR:
case amdgpu_gfx90a::SGPR_VEC2:
case amdgpu_gfx90a::SGPR_VEC4:
case amdgpu_gfx90a::SGPR_VEC8:
case amdgpu_gfx90a::SGPR_VEC16:
return MachRegister( (reg & 0x000000ff) | amdgpu_gfx90a::s0);
case amdgpu_gfx90a::VGPR:
case amdgpu_gfx90a::VGPR_VEC2:
case amdgpu_gfx90a::VGPR_VEC4:
case amdgpu_gfx90a::VGPR_VEC8:
case amdgpu_gfx90a::VGPR_VEC16:
return MachRegister( (reg & 0x000000ff) | amdgpu_gfx90a::v0);
case amdgpu_gfx90a::HWR:
return MachRegister(reg);
Expand All @@ -133,17 +117,9 @@ MachRegister MachRegister::getBaseRegister() const {
case Arch_amdgpu_gfx940:
switch (category){
case amdgpu_gfx940::SGPR:
case amdgpu_gfx940::SGPR_VEC2:
case amdgpu_gfx940::SGPR_VEC4:
case amdgpu_gfx940::SGPR_VEC8:
case amdgpu_gfx940::SGPR_VEC16:
return MachRegister( (reg & 0x000000ff) | amdgpu_gfx940::s0);
case amdgpu_gfx940::VGPR:
case amdgpu_gfx940::VGPR_VEC2:
case amdgpu_gfx940::VGPR_VEC4:
case amdgpu_gfx940::VGPR_VEC8:
case amdgpu_gfx940::VGPR_VEC16:
return MachRegister( (reg & 0x000000ff) | amdgpu_gfx940::v0);
return MachRegister( (reg & 0x000000ff) | amdgpu_gfx940::v0);
case amdgpu_gfx940::HWR:
return MachRegister(reg);

Expand Down Expand Up @@ -280,14 +256,6 @@ unsigned int MachRegister::size() const {
int reg_class = (reg&0x00ff0000 ) ;
if ( reg_class == amdgpu_gfx908::SGPR || reg_class == amdgpu_gfx908::VGPR){
return 4;
}else if (reg_class == amdgpu_gfx908::SGPR_VEC2 || reg_class == amdgpu_gfx908::VGPR_VEC2){
return 8;
}else if (reg_class == amdgpu_gfx908::SGPR_VEC4 || reg_class == amdgpu_gfx908::VGPR_VEC4){
return 16;
}else if (reg_class == amdgpu_gfx908::SGPR_VEC8 || reg_class == amdgpu_gfx908::VGPR_VEC8){
return 32;
}else if (reg_class == amdgpu_gfx908::SGPR_VEC16 || reg_class == amdgpu_gfx908::VGPR_VEC16){
return 64;
}else{
switch(reg & 0x00007f00){
case amdgpu_gfx908::BITS_1:
Expand Down Expand Up @@ -323,14 +291,6 @@ unsigned int MachRegister::size() const {
int reg_class = (reg&0x00ff0000 ) ;
if ( reg_class == amdgpu_gfx90a::SGPR || reg_class == amdgpu_gfx90a::VGPR){
return 4;
}else if (reg_class == amdgpu_gfx90a::SGPR_VEC2 || reg_class == amdgpu_gfx90a::VGPR_VEC2){
return 8;
}else if (reg_class == amdgpu_gfx90a::SGPR_VEC4 || reg_class == amdgpu_gfx90a::VGPR_VEC4){
return 16;
}else if (reg_class == amdgpu_gfx90a::SGPR_VEC8 || reg_class == amdgpu_gfx90a::VGPR_VEC8){
return 32;
}else if (reg_class == amdgpu_gfx90a::SGPR_VEC16 || reg_class == amdgpu_gfx90a::VGPR_VEC16){
return 64;
}else{
switch(reg & 0x00007f00){
case amdgpu_gfx90a::BITS_1:
Expand Down Expand Up @@ -366,14 +326,6 @@ unsigned int MachRegister::size() const {
int reg_class = (reg&0x00ff0000 ) ;
if ( reg_class == amdgpu_gfx940::SGPR || reg_class == amdgpu_gfx940::VGPR){
return 4;
}else if (reg_class == amdgpu_gfx940::SGPR_VEC2 || reg_class == amdgpu_gfx940::VGPR_VEC2){
return 8;
}else if (reg_class == amdgpu_gfx940::SGPR_VEC4 || reg_class == amdgpu_gfx940::VGPR_VEC4){
return 16;
}else if (reg_class == amdgpu_gfx940::SGPR_VEC8 || reg_class == amdgpu_gfx940::VGPR_VEC8){
return 32;
}else if (reg_class == amdgpu_gfx940::SGPR_VEC16 || reg_class == amdgpu_gfx940::VGPR_VEC16){
return 64;
}else{
switch(reg & 0x00007f00){
case amdgpu_gfx940::BITS_1:
Expand Down

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