Significant fixes to John Mellor-Crummey's binary parsing issue.

dyninst · Jun 10, 2016 · 169bdeb · 169bdeb
1 parent 4f70d02
commit 169bdeb
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Showing 3 changed files with 38 additions and 12 deletions.
diff --git a/common/h/entryIDs.h b/common/h/entryIDs.h
@@ -170,6 +170,7 @@ enum entryID {
   e_divsd,
   e_divss,
   e_dppd,	// SSE 4.1
+  e_vdppd,	// SSE 4.1
   e_dpps,	// SSE 4.1
   e_emms,
   e_enter,

diff --git a/common/src/arch-x86.C b/common/src/arch-x86.C
@@ -107,6 +107,7 @@ enum {
 enum {
     SSEVEX41 = 0, SSEVEX42, SSEVEX44, SSEVEX45, SSEVEX46, SSEVEX47,
     SSEVEX4A, SSEVEX4B,
+    SSEVEX73, 
     SSEVEX78,
     SSEVEX90, SSEVEX91, SSEVEX93, 
     SSEVEX98, SSEVEX99
@@ -248,7 +249,7 @@ SSEB00 = 0, SSEB01, SSEB02, SSEB03, SSEB04, SSEB05, SSEB06, SSEB07,
     SSEB58, SSEB59, SSEB5A,
                                             SSEB65, SSEB66,
                                             SSEB75, SSEB76, SSEB77,
-    SSEB78, SSEB79,                         SSEB7D, SSEB7E, SSEB7F,
+    SSEB78, SSEB79,                 SSEB7C, SSEB7D, SSEB7E, SSEB7F,
                             SSEB83,
     SSEB88, SSEB89,         SSEB8B, SSEB8C, SSEB8D, SSEB8E,
     SSEB90, SSEB91, SSEB92, SSEB93,
@@ -338,6 +339,7 @@ enum { /** AUTOGENERATED */
     SSEB75_66,
     SSEB76_66,
     SSEB77_66,
+    SSEB7C_66,
     SSEB7D_66,
     SSEB7E_66,
     SSEB7F_66,
@@ -519,11 +521,11 @@ VEXW00 = 0, VEXW01, VEXW02, VEXW03, VEXW04, VEXW05, VEXW06, VEXW07,
   VEXW78, VEXW79, VEXW7A, VEXW7B, VEXW7C, VEXW7D, VEXW7E, VEXW7F,
   VEXW80, VEXW81, VEXW82, VEXW83, VEXW84, VEXW85, VEXW86, VEXW87,
   VEXW88, VEXW89, VEXW8A, VEXW8B, VEXW8C, VEXW8D, VEXW8E, VEXW8F,
-  VEXW90, VEXW91, VEXW92
+  VEXW90, VEXW91, VEXW92, VEXW93, VEXW94
 };
 /** END_DYNINST_TABLE_DEF */
 
-#define VEXW_MAX VEXW92
+#define VEXW_MAX VEXW94
 
 /* SIMD op conversion table */
 static char vex3_simdop_convert[3][4] = {
@@ -827,6 +829,7 @@ COMMON_EXPORT dyn_hash_map<entryID, std::string> entryNames_IAPI = map_list_of
   (e_divsd, "divsd")
   (e_divss, "divss")
   (e_dppd, "dppd")
+  (e_vdppd, "vdppd")
   (e_dpps, "dpps")
   (e_emms, "emms")
   (e_enter, "enter")
@@ -2493,7 +2496,7 @@ static ia32_entry twoByteMap[256] = {
   { e_No_Entry, t_sse, SSE70, true, { Zz, Zz, Zz }, 0, 0 },
   { e_No_Entry, t_grp, Grp12, false, { Zz, Zz, Zz }, 0, 0 },
   { e_No_Entry, t_grp, Grp13, false, { Zz, Zz, Zz }, 0, 0 },
-  { e_No_Entry, t_grp, Grp14, false, { Zz, Zz, Zz }, 0, 0 },
+  { e_No_Entry, t_sse_vex_mult, SSEVEX73, false, { Zz, Zz, Zz }, 0, 0 },
   { e_No_Entry, t_sse, SSE74, true, { Zz, Zz, Zz }, 0, 0 },
   { e_No_Entry, t_sse, SSE75, true, { Zz, Zz, Zz }, 0, 0 },
   { e_No_Entry, t_sse, SSE76, true, { Zz, Zz, Zz }, 0, 0 },
@@ -2797,7 +2800,7 @@ static ia32_entry threeByteMap[256] = {
 		{ e_No_Entry, t_sse_bis, SSEB79, false, { Zz, Zz, Zz }, 0, 0 },
 		{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
 		{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
-		{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
+		{ e_No_Entry, t_sse_bis, SSEB7C, false, { Zz, Zz, Zz }, 0, 0 },
 		{ e_No_Entry, t_sse_bis, SSEB7D, false, { Zz, Zz, Zz }, 0, 0 },
 		{ e_No_Entry, t_sse_bis, SSEB7E, false, { Zz, Zz, Zz }, 0, 0 },
 		{ e_No_Entry, t_sse_bis, SSEB7F, false, { Zz, Zz, Zz }, 0, 0 },
@@ -3793,6 +3796,11 @@ static ia32_entry sseVexMult[][4] = {
         { e_No_Entry, t_sse, SSE4B, false, { Zz, Zz, Zz }, 0, 0 },
         { e_No_Entry, t_sse, SSE4B, false, { Zz, Zz, Zz }, 0, 0 },
         { e_No_Entry, t_sse, SSE4B, false, { Zz, Zz, Zz }, 0, 0 },
+    }, { /* SSEVEX73 */
+        { e_No_Entry, t_grp, Grp14, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_sse_mult, SSE73_66, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_sse_mult, SSE73_66, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_sse_mult, SSE73_66, false, { Zz, Zz, Zz }, 0, 0 },
     }, { /* SSEVEX78 */
         { e_No_Entry, t_grp, Grp17, false, { Zz, Zz, Zz }, 0, 0 },
         { e_No_Entry, t_sse_mult, SSE78_66, false, { Zz, Zz, Zz }, 0, 0 },
@@ -3820,9 +3828,9 @@ static ia32_entry sseVexMult[][4] = {
         { e_No_Entry, t_sse, SSE98, false, { Zz, Zz, Zz }, 0, 0 }
     }, { /* SSEVEX99 */
         { e_setns,  t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS) },
-        { e_No_Entry, t_sse, SSE98, false, { Zz, Zz, Zz }, 0, 0 },
-        { e_No_Entry, t_sse, SSE98, false, { Zz, Zz, Zz }, 0, 0 },
-        { e_No_Entry, t_sse, SSE98, false, { Zz, Zz, Zz }, 0, 0 }
+        { e_No_Entry, t_sse, SSE99, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_sse, SSE99, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_sse, SSE99, false, { Zz, Zz, Zz }, 0, 0 }
     }
 };
 /* END_DYNINST_TABLE_VERIFICATION */
@@ -5138,6 +5146,12 @@ static ia32_entry sseMapBis[][5] = {
         { e_vpbroadcastw, t_done, 0, true, { Vps, Ww, Zz }, 0, s1W2R },
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
+    }, { /* SSEB7C */
+        { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_sse_bis_mult, SSEB7C_66, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
     }, { /* SSEB7D */
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
@@ -5580,8 +5594,8 @@ static ia32_entry sseMapTer[][3] =
         { e_blendps, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R },
     }, { /* SSET0D */
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
-        { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
-        { e_blendps, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R },
+        { e_No_Entry, t_vexw, VEXW94, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_No_Entry, t_vexw, VEXW94, false, { Zz, Zz, Zz }, 0, 0 }
     }, { /* SSET0E */
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
@@ -5708,7 +5722,7 @@ static ia32_entry sseMapTer[][3] =
         { e_dpps, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R }, 
     }, { /* SSET41 */
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
-        { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
+        { e_vdppd, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R }, 
         { e_dppd, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R }, 
     }, { /* SSET42 */
         { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
@@ -6332,7 +6346,7 @@ ia32_entry sseMapMult[][3] =
     { e_kmovd, t_done, 0, true, { VK, HK, WK }, 0, s1W2R3R },
     { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
   }, { /* SSE90_NO */
-    { e_kmovw, t_done, 0, true, { VK, HK, WK }, 0, s1W2R3R },
+    { e_kmovw, t_done, 0, true, { VK, WK, Zz }, 0, s1W2R },
     { e_kmovq, t_done, 0, true, { VK, HK, WK }, 0, s1W2R3R },
     { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
   }, { /* SSE91_66 */
@@ -6956,6 +6970,10 @@ ia32_entry sseMapBisMult[][3] =
     { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
     { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
     { e_No_Entry, t_vexw, VEXW6A, false, { Zz, Zz, Zz }, 0, 0 }
+  }, { /* SSEB7C_66 */
+    { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
+    { e_No_Entry, t_vexw, VEXW93, false, { Zz, Zz, Zz }, 0, 0 },
+    { e_No_Entry, t_vexw, VEXW93, false, { Zz, Zz, Zz }, 0, 0 }
   }, { /* SSEB7D_66 */
     { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
     { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
@@ -8030,6 +8048,12 @@ static struct ia32_entry vexWMap[][2] =
     }, { /* VEXW92 */
       { e_vgatherdps, t_done, 0, true, { Wss, Vss, Zz }, 0, s1RW2R }, /* W = 0 */
       { e_vgatherdpd, t_done, 0, true, { Wsd, Vsd, Zz }, 0, s1RW2R }  /* W = 1 */
+    }, { /* VEXW93 */
+      { e_vpbroadcastd, t_done, 0, true, { Vps, Wq, Zz }, 0, s1W2R }, /* W = 0 */
+      { e_vpbroadcastq, t_done, 0, true, { Vps, Wq, Zz }, 0, s1W2R }  /* W = 1 */
+    }, { /* VEXW94 */
+      { e_blendps, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R }, /* W = 0 */
+      { e_blendpd, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R }, /* W = 1 */
     }
 };
 /** END_DYNINST_TABLE_VERIFICATION */

diff --git a/instructionAPI/src/InstructionDecoder-x86.C b/instructionAPI/src/InstructionDecoder-x86.C
@@ -831,6 +831,7 @@ namespace Dyninst
                 break;
             default:  break;/** SSE instruction */
         }
+
 #ifdef VEX_DEBUG
         printf("VEX OPERAND:  REGNUM: %d  ", regnum);
 #endif