Add support for formatting consecutive registers as a single operand str

dyninst · Nov 30, 2022 · 27d5059 · 27d5059
1 parent 4ba919a
commit 27d5059
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Showing 10 changed files with 6,342 additions and 6,307 deletions.
diff --git a/instructionAPI/h/Register.h b/instructionAPI/h/Register.h
@@ -55,9 +55,9 @@ namespace Dyninst
       typedef boost::shared_ptr<RegisterAST> Ptr;
 
       /// Construct a register, assigning it the ID \c id.
-      RegisterAST(MachRegister r);
-      RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit);
-      RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType);
+      RegisterAST(MachRegister r, uint32_t num_elements = 1 );
+      RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, uint32_t num_elements = 1);
+      RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType, uint32_t num_elements = 1);
 
       virtual ~RegisterAST();
 
@@ -113,6 +113,7 @@ namespace Dyninst
       MachRegister m_Reg;
       unsigned int m_Low;
       unsigned int m_High;
+      unsigned int m_num_elements;
     };
 
     /**

diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C
@@ -206,7 +206,6 @@ namespace Dyninst {
 		void InstructionDecoder_amdgpu_gfx908::reset(){
 			immLen = 0;
 			insn_size = 0;
-			num_elements =1;
 			isBranch = false;
 			isConditional = false;
 			isModifyPC =false;

diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h
@@ -211,7 +211,6 @@ namespace Dyninst {
 
 #define IS_LD_ST() (isLoad || isStore )
 
-            unsigned int num_elements{1};  // the number of elements that will be load or store by each instruction
             bool isSMEM{}; // this is set when using smem instruction
             bool isLoad{}; // this is set when a smem instruction is load, will set number of elements that are loaded at the same time
             bool isStore{}; // similar to isLoad, but for store instructions
@@ -266,12 +265,6 @@ namespace Dyninst {
 
 
 
-            template<unsigned int num_elements>
-                void setLoad(){isLoad = true; this->num_elements = num_elements; }
-
-            template<unsigned int num_elements>
-                void setStore() {isStore = true;this->num_elements = num_elements;}
-
             void setScratch() {isScratch = true;}
 
             void setBuffer() {isBuffer = true;}

diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C
diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h
@@ -1,41 +1,41 @@
-Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_ATTR(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_PARAM(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SGPR(uint64_t input, uint32_t opr_size );
+Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_ATTR(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_PARAM(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SGPR(uint64_t input, uint32_t num_elements = 1 );
 void processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout  );
-Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_TGT(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_TRAP(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size );
-Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size );
+Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_TGT(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_TRAP(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t num_elements = 1 );
+Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t num_elements = 1 );